Dwayne C. Jones

Array ( [id] => 19805250 [patent_doc_number] => 20250071175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => BLOCKCHAIN SHARDING METHOD AND SYSTEM BASED ON CONVOLUTIONAL NEURAL NETWORK-LONG SHORT-TERM MEMORY (CNN-LSTM) PREDICTION MODEL [patent_app_type] => utility [patent_app_number] => 18/384405 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19114858 [patent_doc_number] => 20240126608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => VALIDATION SYSTEM FOR EXECUTING A METHOD FOR PRIORITIZING VALIDATION TASKS [patent_app_type] => utility [patent_app_number] => 18/380378 [patent_app_country] => US [patent_app_date] => 2023-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18380378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18160678 [patent_doc_number] => 20230027270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => METHODS OF CHEMICAL COMPUTATION [patent_app_type] => utility [patent_app_number] => 17/929279 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17929279 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10009732 [patent_doc_number] => 09053253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Safety arrangement' [patent_app_type] => utility [patent_app_number] => 14/455692 [patent_app_country] => US [patent_app_date] => 2014-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3559 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14455692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10027583 [patent_doc_number] => 09069483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'System and method for monitoring two-wire communication in a network environment' [patent_app_type] => utility [patent_app_number] => 14/336511 [patent_app_country] => US [patent_app_date] => 2014-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14336511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9700629 [patent_doc_number] => 20140250314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'SYSTEM AND METHOD FOR PROVIDING A LOW POWER REMOTE CONTROL' [patent_app_type] => utility [patent_app_number] => 14/276498 [patent_app_country] => US [patent_app_date] => 2014-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4801 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14276498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9834423 [patent_doc_number] => 08943256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-27 [patent_title] => 'Serial data intermediary device, and related systems and methods' [patent_app_type] => utility [patent_app_number] => 14/133359 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 9229 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9200459 [patent_doc_number] => 20130339774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'IMAGE FORMING APPARATUS AND POWER MANAGEMENT METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/972357 [patent_app_country] => US [patent_app_date] => 2013-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7588 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13972357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9200248 [patent_doc_number] => 20130339563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'SYSTEMS AND METHODS FOR ADVANCED INTERRUPT SCHEDULING AND PRIORITY PROCESSING IN A STORAGE SYSTEM ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 13/969733 [patent_app_country] => US [patent_app_date] => 2013-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13969733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9137128 [patent_doc_number] => 20130297843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Computer System' [patent_app_type] => utility [patent_app_number] => 13/891501 [patent_app_country] => US [patent_app_date] => 2013-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1850 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13891501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9372372 [patent_doc_number] => 20140082245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'METHOD AND SERVER FOR MANAGING REDUNDANT ARRAYS OF INDEPENDENT DISKS CARDS' [patent_app_type] => utility [patent_app_number] => 13/858030 [patent_app_country] => US [patent_app_date] => 2013-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2162 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13858030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9707391 [patent_doc_number] => 08832485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Method and apparatus for cache control' [patent_app_type] => utility [patent_app_number] => 13/854616 [patent_app_country] => US [patent_app_date] => 2013-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12213 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13854616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9527431 [patent_doc_number] => 08751722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)' [patent_app_type] => utility [patent_app_number] => 13/851337 [patent_app_country] => US [patent_app_date] => 2013-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2625 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13851337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9758736 [patent_doc_number] => 20140289437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'EXPANDER INTERRUPT PROCESSING' [patent_app_type] => utility [patent_app_number] => 13/849616 [patent_app_country] => US [patent_app_date] => 2013-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13849616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8991915 [patent_doc_number] => 20130219196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'POWER MANAGEMENT FOR MULTIPLE PROCESSOR CORES' [patent_app_type] => utility [patent_app_number] => 13/847392 [patent_app_country] => US [patent_app_date] => 2013-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5806 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13847392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9752200 [patent_doc_number] => 08843689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-23 [patent_title] => 'Concurrent repair of the PCIe switch units in a tightly-coupled, multi-switch, multi-adapter, multi-host distributed system' [patent_app_type] => utility [patent_app_number] => 13/792957 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7448 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9688112 [patent_doc_number] => 20140244877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'Emulating Level Triggered Interrupts of Physical Devices Assigned to a Virtual Machine' [patent_app_type] => utility [patent_app_number] => 13/776288 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9688110 [patent_doc_number] => 20140244875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'Priority Based Connection Arbitration in a SAS Topology to Facilitate Quality of Service (QoS) in SAS Transport' [patent_app_type] => utility [patent_app_number] => 13/776160 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2820 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10100680 [patent_doc_number] => 09137005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Managing arbitration in mixed link rate wide ports' [patent_app_type] => utility [patent_app_number] => 13/763152 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13763152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9365196 [patent_doc_number] => 20140075070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'SIGNAL TRANSMISSION METHOD FOR USB INTERFACE AND APPARATUS THEREOF' [patent_app_type] => utility [patent_app_number] => 13/761323 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761323 [rel_patent_id] =>[rel_patent_doc_number] =>)