
Dwin M. Craig
Examiner (ID: 6007, Phone: (571)272-3710 , Office: P/2123 )
| Most Active Art Unit | 2123 |
| Art Unit(s) | 2123, 2128 |
| Total Applications | 790 |
| Issued Applications | 605 |
| Pending Applications | 33 |
| Abandoned Applications | 153 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5286159
[patent_doc_number] => 20090099834
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'METHOD AND SYSTEM FOR USING STORED DATA ITEMS IN NATIVE DATA FORMATS IN EMULATED E-MODE PROGRAMS'
[patent_app_type] => utility
[patent_app_number] => 12/337707
[patent_app_country] => US
[patent_app_date] => 2008-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4397
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20090099834.pdf
[firstpage_image] =>[orig_patent_app_number] => 12337707
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/337707 | METHOD AND SYSTEM FOR USING STORED DATA ITEMS IN NATIVE DATA FORMATS IN EMULATED E-MODE PROGRAMS | Dec 17, 2008 | Abandoned |
Array
(
[id] => 5547442
[patent_doc_number] => 20090157319
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-18
[patent_title] => 'Systems and Methods for Modeling Wellbore Trajectories'
[patent_app_type] => utility
[patent_app_number] => 12/337408
[patent_app_country] => US
[patent_app_date] => 2008-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7697
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20090157319.pdf
[firstpage_image] =>[orig_patent_app_number] => 12337408
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/337408 | Systems and methods for modeling wellbore trajectories | Dec 16, 2008 | Issued |
Array
(
[id] => 5503508
[patent_doc_number] => 20090164196
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-25
[patent_title] => 'METHOD AND APPARATUS OF CIRCUIT SIMULATION OF HIGH-WITHSTAND-VOLTAGE MOS TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 12/336012
[patent_app_country] => US
[patent_app_date] => 2008-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3777
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20090164196.pdf
[firstpage_image] =>[orig_patent_app_number] => 12336012
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/336012 | METHOD AND APPARATUS OF CIRCUIT SIMULATION OF HIGH-WITHSTAND-VOLTAGE MOS TRANSISTOR | Dec 15, 2008 | Abandoned |
Array
(
[id] => 6347772
[patent_doc_number] => 20100085679
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-08
[patent_title] => 'METHOD FOR USING AN RC CIRCUIT TO MODEL TRAPPED CHARGE IN AN ELECTROSTATIC CHUCK'
[patent_app_type] => utility
[patent_app_number] => 12/333935
[patent_app_country] => US
[patent_app_date] => 2008-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6560
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20100085679.pdf
[firstpage_image] =>[orig_patent_app_number] => 12333935
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/333935 | Method for using an RC circuit to model trapped charge in an electrostatic chuck | Dec 11, 2008 | Issued |
Array
(
[id] => 4519761
[patent_doc_number] => 07917340
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-29
[patent_title] => 'Method and apparatus for importing data into program code'
[patent_app_type] => utility
[patent_app_number] => 12/333547
[patent_app_country] => US
[patent_app_date] => 2008-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3528
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/917/07917340.pdf
[firstpage_image] =>[orig_patent_app_number] => 12333547
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/333547 | Method and apparatus for importing data into program code | Dec 11, 2008 | Issued |
Array
(
[id] => 5369389
[patent_doc_number] => 20090306948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-10
[patent_title] => 'VOLUME SIMULATION'
[patent_app_type] => utility
[patent_app_number] => 12/329333
[patent_app_country] => US
[patent_app_date] => 2008-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4490
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0306/20090306948.pdf
[firstpage_image] =>[orig_patent_app_number] => 12329333
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/329333 | Method, system and computer readable media for deforming simulation meshes used in posing animated characters | Dec 4, 2008 | Issued |
Array
(
[id] => 5423682
[patent_doc_number] => 20090150138
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-11
[patent_title] => 'Apparatus and method for analyzing circuit'
[patent_app_type] => utility
[patent_app_number] => 12/314231
[patent_app_country] => US
[patent_app_date] => 2008-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8084
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0150/20090150138.pdf
[firstpage_image] =>[orig_patent_app_number] => 12314231
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/314231 | Apparatus and method for analyzing circuit | Dec 4, 2008 | Abandoned |
Array
(
[id] => 6251282
[patent_doc_number] => 20100138207
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-03
[patent_title] => 'Method and Apparatus for Circuit Simulation'
[patent_app_type] => utility
[patent_app_number] => 12/326239
[patent_app_country] => US
[patent_app_date] => 2008-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 11199
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0138/20100138207.pdf
[firstpage_image] =>[orig_patent_app_number] => 12326239
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/326239 | Method and Apparatus for Circuit Simulation | Dec 1, 2008 | Abandoned |
Array
(
[id] => 8551696
[patent_doc_number] => 08326588
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-12-04
[patent_title] => 'Fair path selection during simulation of decision nodes'
[patent_app_type] => utility
[patent_app_number] => 12/324342
[patent_app_country] => US
[patent_app_date] => 2008-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5168
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12324342
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/324342 | Fair path selection during simulation of decision nodes | Nov 25, 2008 | Issued |
Array
(
[id] => 6548865
[patent_doc_number] => 20100125444
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-20
[patent_title] => 'Method And Apparatus For Reducing Read Latency In A Pseudo Nor Device'
[patent_app_type] => utility
[patent_app_number] => 12/272710
[patent_app_country] => US
[patent_app_date] => 2008-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2526
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0125/20100125444.pdf
[firstpage_image] =>[orig_patent_app_number] => 12272710
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/272710 | Method And Apparatus For Reducing Read Latency In A Pseudo Nor Device | Nov 16, 2008 | Abandoned |
Array
(
[id] => 6548814
[patent_doc_number] => 20100125440
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-20
[patent_title] => 'Method and Apparatus for Circuit Simulation'
[patent_app_type] => utility
[patent_app_number] => 12/272141
[patent_app_country] => US
[patent_app_date] => 2008-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 10526
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0125/20100125440.pdf
[firstpage_image] =>[orig_patent_app_number] => 12272141
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/272141 | Method and Apparatus for Circuit Simulation | Nov 16, 2008 | Abandoned |
Array
(
[id] => 6326342
[patent_doc_number] => 20100114347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-06
[patent_title] => 'SYSTEMS AND METHODS FOR EVENT BASED EXECUTION OF FIELDBUS PROCESS CONTROL STRATEGIES'
[patent_app_type] => utility
[patent_app_number] => 12/266017
[patent_app_country] => US
[patent_app_date] => 2008-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8031
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0114/20100114347.pdf
[firstpage_image] =>[orig_patent_app_number] => 12266017
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/266017 | Systems and methods for event based execution of fieldbus process control strategies | Nov 5, 2008 | Issued |
Array
(
[id] => 8218924
[patent_doc_number] => 08195439
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-06-05
[patent_title] => 'Real-time adaptive circuit simulation'
[patent_app_type] => utility
[patent_app_number] => 12/264246
[patent_app_country] => US
[patent_app_date] => 2008-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 26
[patent_no_of_words] => 14102
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/195/08195439.pdf
[firstpage_image] =>[orig_patent_app_number] => 12264246
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/264246 | Real-time adaptive circuit simulation | Nov 2, 2008 | Issued |
Array
(
[id] => 7745298
[patent_doc_number] => 08108188
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-31
[patent_title] => 'Enumerated linear programming for optimal strategies'
[patent_app_type] => utility
[patent_app_number] => 12/261616
[patent_app_country] => US
[patent_app_date] => 2008-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4870
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/108/08108188.pdf
[firstpage_image] =>[orig_patent_app_number] => 12261616
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/261616 | Enumerated linear programming for optimal strategies | Oct 29, 2008 | Issued |
Array
(
[id] => 7552791
[patent_doc_number] => 08065132
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-22
[patent_title] => 'Computer-implemented systems and methods for augmenting stochastic event simulations for design of experiments'
[patent_app_type] => utility
[patent_app_number] => 12/259679
[patent_app_country] => US
[patent_app_date] => 2008-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 23
[patent_no_of_words] => 5418
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/065/08065132.pdf
[firstpage_image] =>[orig_patent_app_number] => 12259679
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/259679 | Computer-implemented systems and methods for augmenting stochastic event simulations for design of experiments | Oct 27, 2008 | Issued |
Array
(
[id] => 9129706
[patent_doc_number] => 08577662
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-05
[patent_title] => 'Method of determining the particle sensitivity of electronic components'
[patent_app_type] => utility
[patent_app_number] => 12/739632
[patent_app_country] => US
[patent_app_date] => 2008-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 5070
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12739632
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/739632 | Method of determining the particle sensitivity of electronic components | Oct 22, 2008 | Issued |
Array
(
[id] => 5586792
[patent_doc_number] => 20090105994
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-23
[patent_title] => 'Electronic Floor Plan Server and Method'
[patent_app_type] => utility
[patent_app_number] => 12/249516
[patent_app_country] => US
[patent_app_date] => 2008-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5259
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0105/20090105994.pdf
[firstpage_image] =>[orig_patent_app_number] => 12249516
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/249516 | Electronic floor plan server and method | Oct 9, 2008 | Issued |
Array
(
[id] => 8119245
[patent_doc_number] => 08160843
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-17
[patent_title] => 'Device and method for planning a production unit'
[patent_app_type] => utility
[patent_app_number] => 12/287206
[patent_app_country] => US
[patent_app_date] => 2008-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1603
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/160/08160843.pdf
[firstpage_image] =>[orig_patent_app_number] => 12287206
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/287206 | Device and method for planning a production unit | Oct 6, 2008 | Issued |
Array
(
[id] => 8272679
[patent_doc_number] => 08214193
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-03
[patent_title] => 'Virtualized policy tester'
[patent_app_type] => utility
[patent_app_number] => 12/243608
[patent_app_country] => US
[patent_app_date] => 2008-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4221
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12243608
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/243608 | Virtualized policy tester | Sep 30, 2008 | Issued |
Array
(
[id] => 5429727
[patent_doc_number] => 20090089037
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'Method and apparatus for circuit simulation in view of stress exerted on MOS transistor'
[patent_app_type] => utility
[patent_app_number] => 12/285215
[patent_app_country] => US
[patent_app_date] => 2008-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10221
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0089/20090089037.pdf
[firstpage_image] =>[orig_patent_app_number] => 12285215
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/285215 | Method and apparatus for circuit simulation in view of stress exerted on MOS transistor | Sep 29, 2008 | Abandoned |