Search

Dzung C. Nguyen

Examiner (ID: 6042)

Most Active Art Unit
2783
Art Unit(s)
2183, 2302, 2652, 2783
Total Applications
383
Issued Applications
298
Pending Applications
26
Abandoned Applications
59

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3506227 [patent_doc_number] => 05537605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Method and apparatus for controlling at least one piece of equipment' [patent_app_type] => 1 [patent_app_number] => 8/376680 [patent_app_country] => US [patent_app_date] => 1995-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7210 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537605.pdf [firstpage_image] =>[orig_patent_app_number] => 376680 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/376680
Method and apparatus for controlling at least one piece of equipment Jan 22, 1995 Issued
Array ( [id] => 4018005 [patent_doc_number] => 05859995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method and apparatus for coordinating combinatorial logic-clocked state machines' [patent_app_type] => 1 [patent_app_number] => 8/373689 [patent_app_country] => US [patent_app_date] => 1995-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2088 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859995.pdf [firstpage_image] =>[orig_patent_app_number] => 373689 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/373689
Method and apparatus for coordinating combinatorial logic-clocked state machines Jan 16, 1995 Issued
08/369563 METHOD AND APPARATUS FOR REWORKING PRINTED CIRCUIT BOARDS USING SURFACE COATING AND SELECTIVE REMOVAL OF AN ELECTRICALLY CONDUCTIVE MATERIAL Jan 5, 1995 Abandoned
08/343202 PROGRAMMABLE LOGIC WITH OUTPUT BLOCKS HAVING INDEPENDENTLY SELECTABLE OUTPUT VOLTAGES Nov 21, 1994 Abandoned
Array ( [id] => 3709459 [patent_doc_number] => 05678055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Method and device for generating Grobner bases to reduce memory usage and increase computing speed' [patent_app_type] => 1 [patent_app_number] => 8/343912 [patent_app_country] => US [patent_app_date] => 1994-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 12587 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/678/05678055.pdf [firstpage_image] =>[orig_patent_app_number] => 343912 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/343912
Method and device for generating Grobner bases to reduce memory usage and increase computing speed Nov 16, 1994 Issued
Array ( [id] => 3603091 [patent_doc_number] => 05488734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'Coupler for providing a high speed interface between a communication controller and a controller extension' [patent_app_type] => 1 [patent_app_number] => 8/333932 [patent_app_country] => US [patent_app_date] => 1994-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3894 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488734.pdf [firstpage_image] =>[orig_patent_app_number] => 333932 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/333932
Coupler for providing a high speed interface between a communication controller and a controller extension Nov 2, 1994 Issued
Array ( [id] => 3567021 [patent_doc_number] => 05574933 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Task flow computer architecture' [patent_app_type] => 1 [patent_app_number] => 8/329719 [patent_app_country] => US [patent_app_date] => 1994-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 8293 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574933.pdf [firstpage_image] =>[orig_patent_app_number] => 329719 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/329719
Task flow computer architecture Oct 25, 1994 Issued
Array ( [id] => 3716103 [patent_doc_number] => 05675741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Method and apparatus for determining a communications path between two nodes in an Internet Protocol (IP) network' [patent_app_type] => 1 [patent_app_number] => 8/328513 [patent_app_country] => US [patent_app_date] => 1994-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3335 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675741.pdf [firstpage_image] =>[orig_patent_app_number] => 328513 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/328513
Method and apparatus for determining a communications path between two nodes in an Internet Protocol (IP) network Oct 24, 1994 Issued
08/328810 METHOD AND APPARATUS FOR AUTOMATICALLY POPULATING A NETWORK SIMULATOR TOOL Oct 24, 1994 Abandoned
Array ( [id] => 3660906 [patent_doc_number] => 05630155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Portable computer system with mechanism for accumulating mechanical energy for powering the system' [patent_app_type] => 1 [patent_app_number] => 8/323698 [patent_app_country] => US [patent_app_date] => 1994-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 6419 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/630/05630155.pdf [firstpage_image] =>[orig_patent_app_number] => 323698 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/323698
Portable computer system with mechanism for accumulating mechanical energy for powering the system Oct 17, 1994 Issued
08/324857 COMPUTER ARCHITECTURE FOR REDUCING DELAYS DUE TO BRANCH INSTRUCTIONS Oct 17, 1994 Abandoned
Array ( [id] => 3500940 [patent_doc_number] => 05475856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Dynamic multi-mode parallel processing array' [patent_app_type] => 1 [patent_app_number] => 8/324295 [patent_app_country] => US [patent_app_date] => 1994-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6878 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475856.pdf [firstpage_image] =>[orig_patent_app_number] => 324295 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/324295
Dynamic multi-mode parallel processing array Oct 16, 1994 Issued
Array ( [id] => 3567057 [patent_doc_number] => 05519881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Priority encoder for accessing multiple registers simultaneously and a data processing system which uses it' [patent_app_type] => 1 [patent_app_number] => 8/324313 [patent_app_country] => US [patent_app_date] => 1994-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 36 [patent_no_of_words] => 14074 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519881.pdf [firstpage_image] =>[orig_patent_app_number] => 324313 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/324313
Priority encoder for accessing multiple registers simultaneously and a data processing system which uses it Oct 16, 1994 Issued
Array ( [id] => 3759423 [patent_doc_number] => 05754874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Digital signal processor with selective sound operation' [patent_app_type] => 1 [patent_app_number] => 8/322353 [patent_app_country] => US [patent_app_date] => 1994-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3822 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754874.pdf [firstpage_image] =>[orig_patent_app_number] => 322353 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/322353
Digital signal processor with selective sound operation Oct 12, 1994 Issued
08/320280 METHOD AND APPARATUS FOR HANDLING INTERRUPTS IN A MULTIPROCESSOR COMPUTER SYSTEM Oct 6, 1994 Abandoned
Array ( [id] => 3632776 [patent_doc_number] => 05642524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Methods for generating N-dimensional hypercube structures and improved such structures' [patent_app_type] => 1 [patent_app_number] => 8/314726 [patent_app_country] => US [patent_app_date] => 1994-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 5699 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642524.pdf [firstpage_image] =>[orig_patent_app_number] => 314726 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/314726
Methods for generating N-dimensional hypercube structures and improved such structures Sep 28, 1994 Issued
Array ( [id] => 3735043 [patent_doc_number] => 05682547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Status management and data transmission in a system comprising peripherals and a controller thereof' [patent_app_type] => 1 [patent_app_number] => 8/312994 [patent_app_country] => US [patent_app_date] => 1994-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4285 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682547.pdf [firstpage_image] =>[orig_patent_app_number] => 312994 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/312994
Status management and data transmission in a system comprising peripherals and a controller thereof Sep 26, 1994 Issued
Array ( [id] => 3902232 [patent_doc_number] => 05724517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Method for generating a topology map for a serial bus' [patent_app_type] => 1 [patent_app_number] => 8/313679 [patent_app_country] => US [patent_app_date] => 1994-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6384 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724517.pdf [firstpage_image] =>[orig_patent_app_number] => 313679 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/313679
Method for generating a topology map for a serial bus Sep 26, 1994 Issued
08/308774 MICROCONTROLLER SYSTEM FOR PERFORMING OPERATIONS OF MULTIPLE MICROCONTROLLERS Sep 18, 1994 Abandoned
Array ( [id] => 3719067 [patent_doc_number] => 05655135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'System for write protecting a bit that is hardware modified during a read-modify-write cycle' [patent_app_type] => 1 [patent_app_number] => 8/308059 [patent_app_country] => US [patent_app_date] => 1994-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3040 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/655/05655135.pdf [firstpage_image] =>[orig_patent_app_number] => 308059 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/308059
System for write protecting a bit that is hardware modified during a read-modify-write cycle Sep 15, 1994 Issued
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