Dzung Tran

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Array ( [id] => 19590147 [patent_doc_number] => 20240387704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => METHOD OF GAP FILLING FOR SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/785474 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785474 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 20326399 [patent_doc_number] => 20250338487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => MANAGING WORD LINES IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/777925 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18777925 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 20367297 [patent_doc_number] => 20250357109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => BOTTOM-UP GAP FILL USING NON-CONFORMAL POISONING [patent_app_type] => utility [patent_app_number] => 18/666401 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18666401 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 20324669 [patent_doc_number] => 20250336757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => CONCURRENT GENERAL-PURPOSE MEMORY DIE AND NEAR-MEMORY COMPUTE DIE IN SYSTEM-IN-PACKAGE (SIP) [patent_app_type] => utility [patent_app_number] => 18/650269 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650269 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 20088959 [patent_doc_number] => 20250218895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => Integrated Circuit Package Structure with Thermelectric Self-Cooling Device [patent_app_type] => utility [patent_app_number] => 18/643788 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643788 [rel_patent_id] =>[rel_patent_doc_number] =>)

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