Search

Earl N. Taylor

Examiner (ID: 10740, Phone: (571)272-8894 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818, 2896
Total Applications
1234
Issued Applications
1048
Pending Applications
89
Abandoned Applications
135

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17373959 [patent_doc_number] => 20220029011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => Semiconductor Device and Method of Manufacture [patent_app_type] => utility [patent_app_number] => 17/157330 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157330 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157330
Semiconductor device and method of manufacture Jan 24, 2021 Issued
Array ( [id] => 16812470 [patent_doc_number] => 20210135025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => METHOD AND OPTOELECTRONIC STRUCTURE PROVIDING POLYSILICON PHOTONIC DEVICES WITH DIFFERENT OPTICAL PROPERTIES IN DIFFERENT REGIONS [patent_app_type] => utility [patent_app_number] => 17/145301 [patent_app_country] => US [patent_app_date] => 2021-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145301 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145301
Method and optoelectronic structure providing polysilicon photonic devices with different optical properties in different regions Jan 8, 2021 Issued
Array ( [id] => 17723618 [patent_doc_number] => 20220216340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => CONTACT STRUCTURE FOR STACKED MULTI-GATE DEVICE [patent_app_type] => utility [patent_app_number] => 17/140532 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140532
Contact structure for stacked multi-gate device Jan 3, 2021 Issued
Array ( [id] => 16752691 [patent_doc_number] => 20210104703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => DEVICE [patent_app_type] => utility [patent_app_number] => 17/123224 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123224 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123224
Device Dec 15, 2020 Issued
Array ( [id] => 16731248 [patent_doc_number] => 20210098396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/120287 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120287 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120287
Package structure and manufacturing method thereof Dec 13, 2020 Issued
Array ( [id] => 17574221 [patent_doc_number] => 11322496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Method for making field effect transistor and field effect transistor formed [patent_app_type] => utility [patent_app_number] => 17/119887 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6889 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 680 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17119887 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/119887
Method for making field effect transistor and field effect transistor formed Dec 10, 2020 Issued
Array ( [id] => 17607109 [patent_doc_number] => 11335601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Non-planar I/O and logic semiconductor devices having different workfunction on common substrate [patent_app_type] => utility [patent_app_number] => 17/112959 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 7552 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112959 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/112959
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate Dec 3, 2020 Issued
Array ( [id] => 16724056 [patent_doc_number] => 20210091203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/110493 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17110493 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/110493
Semiconductor device and method of manufacturing same Dec 2, 2020 Issued
Array ( [id] => 17668512 [patent_doc_number] => 11362217 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-14 [patent_title] => Method of forming transistors of different configurations [patent_app_type] => utility [patent_app_number] => 17/101212 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101212 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/101212
Method of forming transistors of different configurations Nov 22, 2020 Issued
Array ( [id] => 17630833 [patent_doc_number] => 20220165848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => SOURCE/DRAIN FEATURES [patent_app_type] => utility [patent_app_number] => 17/100543 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100543 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/100543
Source/drain features Nov 19, 2020 Issued
Array ( [id] => 19705163 [patent_doc_number] => 12199211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Process for fabricating a detecting device the getter of which is better protected [patent_app_type] => utility [patent_app_number] => 17/778773 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 8960 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17778773 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/778773
Process for fabricating a detecting device the getter of which is better protected Nov 18, 2020 Issued
Array ( [id] => 17893419 [patent_doc_number] => 11456403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Method of manufacturing a microelectronic device having an array of inclined reliefs [patent_app_type] => utility [patent_app_number] => 16/951357 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 52 [patent_no_of_words] => 10679 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/951357
Method of manufacturing a microelectronic device having an array of inclined reliefs Nov 17, 2020 Issued
Array ( [id] => 16812046 [patent_doc_number] => 20210134601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => INTEGRATED PHOTONIC DEVICE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/090639 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17090639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/090639
Integrated photonic device manufacturing method Nov 4, 2020 Issued
Array ( [id] => 17530127 [patent_doc_number] => 11302828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/084163 [patent_app_country] => US [patent_app_date] => 2020-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 5824 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084163 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/084163
Semiconductor device Oct 28, 2020 Issued
Array ( [id] => 18983720 [patent_doc_number] => 11908910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor device having embedded conductive line and method of fabricating thereof [patent_app_type] => utility [patent_app_number] => 16/949363 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16949363 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/949363
Semiconductor device having embedded conductive line and method of fabricating thereof Oct 26, 2020 Issued
Array ( [id] => 17381292 [patent_doc_number] => 11239325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Semiconductor device having backside via and method of fabricating thereof [patent_app_type] => utility [patent_app_number] => 16/948712 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 87 [patent_no_of_words] => 9717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16948712 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/948712
Semiconductor device having backside via and method of fabricating thereof Sep 28, 2020 Issued
Array ( [id] => 17509432 [patent_doc_number] => 20220102535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => Method of Forming Backside Power Rails [patent_app_type] => utility [patent_app_number] => 17/037274 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037274 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/037274
Method of forming backside power rails Sep 28, 2020 Issued
Array ( [id] => 17310389 [patent_doc_number] => 11211516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Stack-like III-V semiconductor product and production method [patent_app_type] => utility [patent_app_number] => 17/034847 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034847 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/034847
Stack-like III-V semiconductor product and production method Sep 27, 2020 Issued
Array ( [id] => 16560388 [patent_doc_number] => 20210005537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => Sintered Metal Flip Chip Joints [patent_app_type] => utility [patent_app_number] => 17/027657 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/027657
Sintered Metal Flip Chip Joints Sep 20, 2020 Pending
Array ( [id] => 17803453 [patent_doc_number] => 11417766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Transistors having nanostructures [patent_app_type] => utility [patent_app_number] => 17/023125 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 66 [patent_no_of_words] => 10875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023125 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/023125
Transistors having nanostructures Sep 15, 2020 Issued
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