Search

Eddie C. H. Lee

Supervisory Patent Examiner (ID: 11782, Phone: (571)272-1732 , Office: P/2100 )

Most Active Art Unit
2101
Art Unit(s)
2811, 2851, 2101
Total Applications
580
Issued Applications
457
Pending Applications
17
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19123528 [patent_doc_number] => 11967522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Amorphous layers for reducing copper diffusion and method forming same [patent_app_type] => utility [patent_app_number] => 17/660508 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17660508 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/660508
Amorphous layers for reducing copper diffusion and method forming same Apr 24, 2022 Issued
Array ( [id] => 19288256 [patent_doc_number] => 20240224739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => DISPLAY APPARATUS AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/288083 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 53174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18288083 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/288083
DISPLAY APPARATUS AND ELECTRONIC DEVICE Apr 21, 2022 Pending
Array ( [id] => 19900260 [patent_doc_number] => 12278197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Package board [patent_app_type] => utility [patent_app_number] => 17/718725 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4612 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718725 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718725
Package board Apr 11, 2022 Issued
Array ( [id] => 17764821 [patent_doc_number] => 20220238434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => PROTECTION LINER ON INTERCONNECT WIRE TO ENLARGE PROCESSING WINDOW FOR OVERLYING INTERCONNECT VIA [patent_app_type] => utility [patent_app_number] => 17/718461 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718461 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718461
Protection liner on interconnect wire to enlarge processing window for overlying interconnect via Apr 11, 2022 Issued
Array ( [id] => 18696448 [patent_doc_number] => 20230326887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => CLAMPED SEMICONDUCTOR WAFERS AND SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/718021 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718021 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718021
Clamped semiconductor wafers and semiconductor devices Apr 10, 2022 Issued
Array ( [id] => 18804382 [patent_doc_number] => 11837546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Self-aligned cavity strucutre [patent_app_type] => utility [patent_app_number] => 17/714428 [patent_app_country] => US [patent_app_date] => 2022-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 7094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17714428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/714428
Self-aligned cavity strucutre Apr 5, 2022 Issued
Array ( [id] => 18679859 [patent_doc_number] => 20230317517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => INTEGRATED CIRCUIT INTERCONNECT STRUCTURES WITH A METAL CHALCOGENIDE LINER [patent_app_type] => utility [patent_app_number] => 17/711892 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17711892 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/711892
Integrated circuit interconnect structures with a metal chalcogenide liner Mar 31, 2022 Issued
Array ( [id] => 17738012 [patent_doc_number] => 20220223474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => Methods for Forming Self-Aligned Interconnect Structures [patent_app_type] => utility [patent_app_number] => 17/705487 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705487 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705487
Methods for forming self-aligned interconnect structures Mar 27, 2022 Issued
Array ( [id] => 19260872 [patent_doc_number] => 12020937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Carbon implantation for thicker gate silicide [patent_app_type] => utility [patent_app_number] => 17/701759 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5322 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701759
Carbon implantation for thicker gate silicide Mar 22, 2022 Issued
Array ( [id] => 20162958 [patent_doc_number] => 12389615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/695961 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2359 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 478 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695961 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695961
Semiconductor device Mar 15, 2022 Issued
Array ( [id] => 18265531 [patent_doc_number] => 20230086773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/693617 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693617 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/693617
Semiconductor memory device Mar 13, 2022 Issued
Array ( [id] => 18721527 [patent_doc_number] => 11798884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Contact via formation [patent_app_type] => utility [patent_app_number] => 17/682884 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 35 [patent_no_of_words] => 6785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682884 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682884
Contact via formation Feb 27, 2022 Issued
Array ( [id] => 20080830 [patent_doc_number] => 12354907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Electron migration control in interconnect structures [patent_app_type] => utility [patent_app_number] => 17/682823 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 2105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682823 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682823
Electron migration control in interconnect structures Feb 27, 2022 Issued
Array ( [id] => 17660868 [patent_doc_number] => 20220181333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/678429 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17678429 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/678429
Semiconductor storage device and method for producing semiconductor storage device Feb 22, 2022 Issued
Array ( [id] => 20204136 [patent_doc_number] => 12406920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Top via interconnect with airgap [patent_app_type] => utility [patent_app_number] => 17/651432 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 1087 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17651432 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/651432
Top via interconnect with airgap Feb 16, 2022 Issued
Array ( [id] => 18167753 [patent_doc_number] => 20230034360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/671737 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671737
Semiconductor structure and method for forming the same Feb 14, 2022 Issued
Array ( [id] => 19951278 [patent_doc_number] => 12322649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Interconnect structure of semiconductor device [patent_app_type] => utility [patent_app_number] => 17/669665 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 64 [patent_no_of_words] => 15045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669665 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/669665
Interconnect structure of semiconductor device Feb 10, 2022 Issued
Array ( [id] => 18782330 [patent_doc_number] => 11824097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Contact architecture for capacitance reduction and satisfactory contact resistance [patent_app_type] => utility [patent_app_number] => 17/667493 [patent_app_country] => US [patent_app_date] => 2022-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 12990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 420 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17667493 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/667493
Contact architecture for capacitance reduction and satisfactory contact resistance Feb 7, 2022 Issued
Array ( [id] => 18548185 [patent_doc_number] => 11721544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Cut metal gate process for reducing transistor spacing [patent_app_type] => utility [patent_app_number] => 17/588883 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 32 [patent_no_of_words] => 8062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588883 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588883
Cut metal gate process for reducing transistor spacing Jan 30, 2022 Issued
Array ( [id] => 17566606 [patent_doc_number] => 20220130755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => INTERCONNECT STRUCTURE AND MANUFACTURING METHOD FOR THE SAME [patent_app_type] => utility [patent_app_number] => 17/567525 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567525 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/567525
Interconnect structure and manufacturing method for the same Jan 2, 2022 Issued
Menu