Search

Eddie C. H. Lee

Supervisory Patent Examiner (ID: 11782, Phone: (571)272-1732 , Office: P/2100 )

Most Active Art Unit
2101
Art Unit(s)
2811, 2851, 2101
Total Applications
580
Issued Applications
457
Pending Applications
17
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19928273 [patent_doc_number] => 12302584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Embedded ferroelectric memory in high-k first technology [patent_app_type] => utility [patent_app_number] => 18/358216 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 3956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358216 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358216
Embedded ferroelectric memory in high-k first technology Jul 24, 2023 Issued
Array ( [id] => 18757571 [patent_doc_number] => 20230361034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => SEMICONDUCTOR DEVICE HAVING INTER-METAL DIELECTRIC PATTERNS AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/224592 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224592 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/224592
Semiconductor device having inter-metal dielectric patterns and method for fabricating the same Jul 20, 2023 Issued
Array ( [id] => 18943465 [patent_doc_number] => 20240038604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR PRODUCTS [patent_app_type] => utility [patent_app_number] => 18/224805 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224805 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/224805
METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR PRODUCTS Jul 20, 2023 Pending
Array ( [id] => 19855444 [patent_doc_number] => 12258265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Bonding process for forming semiconductor device structure [patent_app_type] => utility [patent_app_number] => 18/354012 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 5256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354012 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354012
Bonding process for forming semiconductor device structure Jul 17, 2023 Issued
Array ( [id] => 20540540 [patent_doc_number] => 12557629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Interconnect structure and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/220886 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 5747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220886 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/220886
Interconnect structure and methods of forming the same Jul 11, 2023 Issued
Array ( [id] => 19696449 [patent_doc_number] => 20250014994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => TERRACED CONDUCTOR STRUCTURE FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/346999 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346999 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346999
TERRACED CONDUCTOR STRUCTURE FOR SEMICONDUCTOR DEVICES Jul 4, 2023 Pending
Array ( [id] => 18898583 [patent_doc_number] => 20240014068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTION STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/217724 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18217724 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/217724
SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTION STRUCTURE Jul 2, 2023 Pending
Array ( [id] => 19206162 [patent_doc_number] => 20240178061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/339569 [patent_app_country] => US [patent_app_date] => 2023-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18339569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/339569
INTEGRATED CIRCUIT DEVICE Jun 21, 2023 Pending
Array ( [id] => 19634561 [patent_doc_number] => 20240413010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/331897 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331897 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/331897
SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME Jun 7, 2023 Pending
Array ( [id] => 19161151 [patent_doc_number] => 20240153858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => CHIP AND ITS MANUFACTURING, MOUNTING METHOD AND PRINTED CIRCUIT BOARD [patent_app_type] => utility [patent_app_number] => 18/331789 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/331789
CHIP AND ITS MANUFACTURING, MOUNTING METHOD AND PRINTED CIRCUIT BOARD Jun 7, 2023 Abandoned
Array ( [id] => 18653063 [patent_doc_number] => 20230298903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => PIT-LESS CHEMICAL MECHANICAL PLANARIZATION PROCESS AND DEVICE STRUCTURES MADE THEREFROM [patent_app_type] => utility [patent_app_number] => 18/325905 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325905 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325905
Pit-less chemical mechanical planarization process and device structures made therefrom May 29, 2023 Issued
Array ( [id] => 18821167 [patent_doc_number] => 20230395508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/202131 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202131 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/202131
SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF May 24, 2023 Pending
Array ( [id] => 19146356 [patent_doc_number] => 20240145386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING CONTACT PLUGS HAVING SILICIDE LAYERS AND METHODS FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/322607 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322607 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/322607
SEMICONDUCTOR DEVICES INCLUDING CONTACT PLUGS HAVING SILICIDE LAYERS AND METHODS FOR FABRICATING THE SAME May 23, 2023 Pending
Array ( [id] => 20532290 [patent_doc_number] => 12550743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Method for producing an individualization zone of an integrated circuit [patent_app_type] => utility [patent_app_number] => 18/318044 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 3546 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 374 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318044 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318044
Method for producing an individualization zone of an integrated circuit May 15, 2023 Issued
Array ( [id] => 19524006 [patent_doc_number] => 12125746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Passivation layer for integrated circuit structure and forming the same [patent_app_type] => utility [patent_app_number] => 18/317759 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18317759 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/317759
Passivation layer for integrated circuit structure and forming the same May 14, 2023 Issued
Array ( [id] => 18615832 [patent_doc_number] => 20230282571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => HYBRID METAL LINE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/313480 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313480 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/313480
Hybrid metal line structure May 7, 2023 Issued
Array ( [id] => 19842695 [patent_doc_number] => 12255095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/310527 [patent_app_country] => US [patent_app_date] => 2023-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 13485 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/310527
Semiconductor structure and manufacturing method thereof Apr 30, 2023 Issued
Array ( [id] => 19546398 [patent_doc_number] => 20240363434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => RAISED SOURCE/DRAIN TRANSISTOR [patent_app_type] => utility [patent_app_number] => 18/308785 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308785 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/308785
Raised source/drain transistor Apr 27, 2023 Issued
Array ( [id] => 19487278 [patent_doc_number] => 12107003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Etch profile control of gate contact opening [patent_app_type] => utility [patent_app_number] => 18/303839 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 59 [patent_no_of_words] => 18496 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303839 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/303839
Etch profile control of gate contact opening Apr 19, 2023 Issued
Array ( [id] => 19720344 [patent_doc_number] => 12205887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Semiconductor device and method for manufacturing the semiconductor device preliminary class [patent_app_type] => utility [patent_app_number] => 18/300700 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 7191 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18300700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/300700
Semiconductor device and method for manufacturing the semiconductor device preliminary class Apr 13, 2023 Issued
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