Search

Eddie C. H. Lee

Supervisory Patent Examiner (ID: 11782, Phone: (571)272-1732 , Office: P/2100 )

Most Active Art Unit
2101
Art Unit(s)
2811, 2851, 2101
Total Applications
580
Issued Applications
457
Pending Applications
17
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19176165 [patent_doc_number] => 20240162139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => METHOD AND STRUCTURE OF FORMING BARRIER-LESS SKIP VIA WITH SUBTRACTIVE METAL PATTERNING [patent_app_type] => utility [patent_app_number] => 18/054187 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18054187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/054187
METHOD AND STRUCTURE OF FORMING BARRIER-LESS SKIP VIA WITH SUBTRACTIVE METAL PATTERNING Nov 9, 2022 Pending
Array ( [id] => 19176113 [patent_doc_number] => 20240162087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => MANDREL-PULL-FIRST INTERCONNECT PATTERNING [patent_app_type] => utility [patent_app_number] => 17/985138 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17985138 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/985138
MANDREL-PULL-FIRST INTERCONNECT PATTERNING Nov 9, 2022 Pending
Array ( [id] => 19356982 [patent_doc_number] => 12057439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Integrated circuit packages [patent_app_type] => utility [patent_app_number] => 17/984379 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 12733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17984379 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/984379
Integrated circuit packages Nov 9, 2022 Issued
Array ( [id] => 19161140 [patent_doc_number] => 20240153847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => METHODS, APPARATUSES, INTEGRATED CIRCUITS, AND CIRCUIT BOARDS FOR POWER CONVERSION WITH REDUCED PARASITICS [patent_app_type] => utility [patent_app_number] => 18/053973 [patent_app_country] => US [patent_app_date] => 2022-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18053973 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/053973
Methods, apparatuses, integrated circuits, and circuit boards for power conversion with reduced parasitics Nov 8, 2022 Issued
Array ( [id] => 18254639 [patent_doc_number] => 20230081678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => ELECTRONIC DEVICES COMPRISING AIR GAPS ADJACENT TO BITLINES [patent_app_type] => utility [patent_app_number] => 18/053626 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18053626 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/053626
Electronic devices comprising air gaps adjacent to bitlines Nov 7, 2022 Issued
Array ( [id] => 20305429 [patent_doc_number] => 12451429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Interconnection structure for a semiconductor device [patent_app_type] => utility [patent_app_number] => 18/053636 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 31 [patent_no_of_words] => 1221 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18053636 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/053636
Interconnection structure for a semiconductor device Nov 7, 2022 Issued
Array ( [id] => 19146346 [patent_doc_number] => 20240145376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => DECOUPLING CAPACITANCE IN BACKSIDE INTERCONNECT [patent_app_type] => utility [patent_app_number] => 18/051028 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051028 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051028
Decoupling capacitance in backside interconnect Oct 30, 2022 Issued
Array ( [id] => 19821203 [patent_doc_number] => 20250079410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => LIGHT-EMITTING SUBSTRATE AND MANUFACTURING METHOD THEREFOR, BACKLIGHT MODULE, AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/553040 [patent_app_country] => US [patent_app_date] => 2022-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18553040 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/553040
LIGHT-EMITTING SUBSTRATE AND MANUFACTURING METHOD THEREFOR, BACKLIGHT MODULE, AND DISPLAY APPARATUS Oct 27, 2022 Pending
Array ( [id] => 18195142 [patent_doc_number] => 20230048661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => CHUCKING PROCESS AND SYSTEM FOR SUBSTRATE PROCESSING CHAMBERS [patent_app_type] => utility [patent_app_number] => 17/975452 [patent_app_country] => US [patent_app_date] => 2022-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17975452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/975452
Chucking process and system for substrate processing chambers Oct 26, 2022 Issued
Array ( [id] => 18309673 [patent_doc_number] => 20230113573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/048633 [patent_app_country] => US [patent_app_date] => 2022-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4649 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18048633 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/048633
Methods for forming conductive vias, and associated devices and systems Oct 20, 2022 Issued
Array ( [id] => 18757569 [patent_doc_number] => 20230361032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => WET RECESS FOR RU SUBTRACTIVE PROCESS [patent_app_type] => utility [patent_app_number] => 17/969440 [patent_app_country] => US [patent_app_date] => 2022-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17969440 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/969440
WET RECESS FOR RU SUBTRACTIVE PROCESS Oct 18, 2022 Pending
Array ( [id] => 18182920 [patent_doc_number] => 20230043650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/964244 [patent_app_country] => US [patent_app_date] => 2022-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17964244 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/964244
Semiconductor device and method of fabricating the same Oct 11, 2022 Issued
Array ( [id] => 18490307 [patent_doc_number] => 20230217661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/961070 [patent_app_country] => US [patent_app_date] => 2022-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961070 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/961070
Semiconductor device and data storage system including the same Oct 5, 2022 Issued
Array ( [id] => 20598187 [patent_doc_number] => 12581927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 17/958295 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 9535 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958295 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958295
Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication Sep 29, 2022 Issued
Array ( [id] => 19086217 [patent_doc_number] => 20240113018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => LOCALLY WIDENED PROFILE FOR NANOSCALE WIRING STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/955803 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7616 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17955803 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/955803
Locally widened profile for nanoscale wiring structure Sep 28, 2022 Issued
Array ( [id] => 18143392 [patent_doc_number] => 20230017241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => ELECTRONIC DEVICES COMPRISING MEMORY PILLARS AND DUMMY PILLARS INCLUDING AN OXIDE MATERIAL, AND RELATED SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 17/933227 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17933227 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/933227
Electronic devices comprising memory pillars and dummy pillars including an oxide material, and related systems and methods Sep 18, 2022 Issued
Array ( [id] => 20146797 [patent_doc_number] => 12381144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/942005 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 4311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17942005 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/942005
Semiconductor device and method of manufacturing the same Sep 8, 2022 Issued
Array ( [id] => 18113216 [patent_doc_number] => 20230006096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => SEMICONDUCTOR LIGHT-EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 17/930109 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17930109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/930109
Semiconductor light-emitting device Sep 6, 2022 Issued
Array ( [id] => 19023176 [patent_doc_number] => 20240079347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => APPARATUSES AND METHODS INCLUDING STRUCTURES IN SCRIBE REGIONS OF SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/930353 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17930353 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/930353
APPARATUSES AND METHODS INCLUDING STRUCTURES IN SCRIBE REGIONS OF SEMICONDUCTOR DEVICES Sep 6, 2022 Pending
Array ( [id] => 19023146 [patent_doc_number] => 20240079317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => TECHNIQUES TO MANUFACTURE INTER-LAYER VIAS [patent_app_type] => utility [patent_app_number] => 17/929973 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17929973 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/929973
Techniques to manufacture inter-layer vias Sep 5, 2022 Issued
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