Search

Eddie C. H. Lee

Supervisory Patent Examiner (ID: 11782, Phone: (571)272-1732 , Office: P/2100 )

Most Active Art Unit
2101
Art Unit(s)
2811, 2851, 2101
Total Applications
580
Issued Applications
457
Pending Applications
17
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20244259 [patent_doc_number] => 12424591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Method and structure of forming independent contact for staggered CFET [patent_app_type] => utility [patent_app_number] => 17/807765 [patent_app_country] => US [patent_app_date] => 2022-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 2390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807765 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/807765
Method and structure of forming independent contact for staggered CFET Jun 19, 2022 Issued
Array ( [id] => 17917524 [patent_doc_number] => 20220319920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => ETCH STOP LAYER FOR MEMORY DEVICE FORMATION [patent_app_type] => utility [patent_app_number] => 17/843145 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17843145 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/843145
Etch stop layer for memory device formation Jun 16, 2022 Issued
Array ( [id] => 17986031 [patent_doc_number] => 20220352068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => SUBTRACTIVELY PATTERNED INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/841551 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841551 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841551
Subtractively patterned interconnect structures for integrated circuits Jun 14, 2022 Issued
Array ( [id] => 18833833 [patent_doc_number] => 20230402360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => POWER PACKAGE HAVING CONNECTED COMPONENTS AND PROCESSES IMPLEMENTING THE SAME [patent_app_type] => utility [patent_app_number] => 17/837640 [patent_app_country] => US [patent_app_date] => 2022-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17837640 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/837640
POWER PACKAGE HAVING CONNECTED COMPONENTS AND PROCESSES IMPLEMENTING THE SAME Jun 9, 2022 Pending
Array ( [id] => 19199088 [patent_doc_number] => 11996337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Substrate processing apparatus, method of manufacturing semiconductor device, and recording medium [patent_app_type] => utility [patent_app_number] => 17/836631 [patent_app_country] => US [patent_app_date] => 2022-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9017 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17836631 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/836631
Substrate processing apparatus, method of manufacturing semiconductor device, and recording medium Jun 8, 2022 Issued
Array ( [id] => 20082561 [patent_doc_number] => 12356659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/834987 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 6936 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834987 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834987
Semiconductor device Jun 7, 2022 Issued
Array ( [id] => 18821165 [patent_doc_number] => 20230395506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SELF-ALIGNED STAGGERED INTEGRATED CIRCUIT INTERCONNECT FEATURES [patent_app_type] => utility [patent_app_number] => 17/833708 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833708 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/833708
SELF-ALIGNED STAGGERED INTEGRATED CIRCUIT INTERCONNECT FEATURES Jun 5, 2022 Pending
Array ( [id] => 19016356 [patent_doc_number] => 11923298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Method of fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 17/830811 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 9578 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17830811 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/830811
Method of fabricating semiconductor device Jun 1, 2022 Issued
Array ( [id] => 17871028 [patent_doc_number] => 20220293765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SEMICONDUCTOR STRUCTURE WITH METAL CAP LAYER AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/830059 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17830059 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/830059
Semiconductor structure with metal cap layer and method for manufacturing the same May 31, 2022 Issued
Array ( [id] => 19262602 [patent_doc_number] => 12022688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Electronic device having an organic light emitting display [patent_app_type] => utility [patent_app_number] => 17/829036 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5263 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829036 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/829036
Electronic device having an organic light emitting display May 30, 2022 Issued
Array ( [id] => 19842830 [patent_doc_number] => 12255232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Gallium nitride drain structures and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/804751 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8678 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804751 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/804751
Gallium nitride drain structures and methods of forming the same May 30, 2022 Issued
Array ( [id] => 17870723 [patent_doc_number] => 20220293460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => Patterning Methods for Semiconductor Devices and Structures Resulting Therefrom [patent_app_type] => utility [patent_app_number] => 17/826352 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826352 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826352
Patterning methods for semiconductor devices and structures resulting therefrom May 26, 2022 Issued
Array ( [id] => 18796935 [patent_doc_number] => 11830770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Self-aligned scheme for semiconductor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/749303 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 7552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749303 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749303
Self-aligned scheme for semiconductor device and method of forming the same May 19, 2022 Issued
Array ( [id] => 18751495 [patent_doc_number] => 11810816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Chemical mechanical polishing topography reset and control on interconnect metal lines [patent_app_type] => utility [patent_app_number] => 17/744545 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 10694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744545 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744545
Chemical mechanical polishing topography reset and control on interconnect metal lines May 12, 2022 Issued
Array ( [id] => 18999072 [patent_doc_number] => 11915927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory computer-readable recording medium [patent_app_type] => utility [patent_app_number] => 17/744380 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 12734 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744380
Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory computer-readable recording medium May 12, 2022 Issued
Array ( [id] => 18969404 [patent_doc_number] => 11903216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Three-dimensional memory device and method [patent_app_type] => utility [patent_app_number] => 17/744212 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 42 [patent_no_of_words] => 11341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744212 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744212
Three-dimensional memory device and method May 12, 2022 Issued
Array ( [id] => 18122515 [patent_doc_number] => 20230008118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/662737 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/662737
Semiconductor structure and manufacturing method thereof May 9, 2022 Issued
Array ( [id] => 17811007 [patent_doc_number] => 20220262842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SOLID-STATE IMAGE SENSOR [patent_app_type] => utility [patent_app_number] => 17/661950 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661950 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/661950
SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SOLID-STATE IMAGE SENSOR May 3, 2022 Abandoned
Array ( [id] => 17810887 [patent_doc_number] => 20220262722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES [patent_app_type] => utility [patent_app_number] => 17/735006 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 85508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735006 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/735006
Advanced lithography and self-assembled devices May 1, 2022 Issued
Array ( [id] => 20638103 [patent_doc_number] => 12599002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Substrate-integrated waveguide [patent_app_type] => utility [patent_app_number] => 17/733921 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733921
SUBSTRATE-INTEGRATED WAVEGUIDE Apr 28, 2022 Issued
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