Search

Eddie P. Chan

Examiner (ID: 4047)

Most Active Art Unit
2307
Art Unit(s)
2307, 2101, 2751, 2183, 2316
Total Applications
716
Issued Applications
479
Pending Applications
12
Abandoned Applications
224

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2677532 [patent_doc_number] => 04954946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-04 [patent_title] => 'Apparatus and method for providing distribution control in a main memory unit of a data processing system' [patent_app_type] => 1 [patent_app_number] => 7/453088 [patent_app_country] => US [patent_app_date] => 1989-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3714 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/954/04954946.pdf [firstpage_image] =>[orig_patent_app_number] => 453088 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/453088
Apparatus and method for providing distribution control in a main memory unit of a data processing system Dec 20, 1989 Issued
Array ( [id] => 2976450 [patent_doc_number] => 05274762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Method for high speed data transfer' [patent_app_type] => 1 [patent_app_number] => 7/451396 [patent_app_country] => US [patent_app_date] => 1989-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 6063 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274762.pdf [firstpage_image] =>[orig_patent_app_number] => 451396 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/451396
Method for high speed data transfer Dec 14, 1989 Issued
Array ( [id] => 2864961 [patent_doc_number] => 05084816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-28 [patent_title] => 'Real time fault tolerant transaction processing system' [patent_app_type] => 1 [patent_app_number] => 7/453042 [patent_app_country] => US [patent_app_date] => 1989-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 22109 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 465 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/084/05084816.pdf [firstpage_image] =>[orig_patent_app_number] => 453042 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/453042
Real time fault tolerant transaction processing system Dec 11, 1989 Issued
Array ( [id] => 2564471 [patent_doc_number] => 04961136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-02 [patent_title] => 'Microprocessor system having cache directory and cache memory and hardware for initializing the directory' [patent_app_type] => 1 [patent_app_number] => 7/443842 [patent_app_country] => US [patent_app_date] => 1989-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1683 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/961/04961136.pdf [firstpage_image] =>[orig_patent_app_number] => 443842 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/443842
Microprocessor system having cache directory and cache memory and hardware for initializing the directory Dec 3, 1989 Issued
Array ( [id] => 2804139 [patent_doc_number] => 05136714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-04 [patent_title] => 'Method and apparatus for implementing inter-processor interrupts using shared memory storage in a multi-processor computer system' [patent_app_type] => 1 [patent_app_number] => 7/445202 [patent_app_country] => US [patent_app_date] => 1989-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4847 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/136/05136714.pdf [firstpage_image] =>[orig_patent_app_number] => 445202 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/445202
Method and apparatus for implementing inter-processor interrupts using shared memory storage in a multi-processor computer system Dec 3, 1989 Issued
Array ( [id] => 2716814 [patent_doc_number] => 05014238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-07 [patent_title] => 'Universal input/output device' [patent_app_type] => 1 [patent_app_number] => 7/442255 [patent_app_country] => US [patent_app_date] => 1989-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4467 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/014/05014238.pdf [firstpage_image] =>[orig_patent_app_number] => 442255 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/442255
Universal input/output device Nov 27, 1989 Issued
Array ( [id] => 2799787 [patent_doc_number] => 05155853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Data processor operating in a vector interrupt mode and register bank switching mode with selected bank for interrupt processing' [patent_app_type] => 1 [patent_app_number] => 7/441146 [patent_app_country] => US [patent_app_date] => 1989-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3773 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155853.pdf [firstpage_image] =>[orig_patent_app_number] => 441146 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/441146
Data processor operating in a vector interrupt mode and register bank switching mode with selected bank for interrupt processing Nov 26, 1989 Issued
Array ( [id] => 2743375 [patent_doc_number] => 05077684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-31 [patent_title] => 'System for accurately informing each of adapters of its packaged location' [patent_app_type] => 1 [patent_app_number] => 7/437694 [patent_app_country] => US [patent_app_date] => 1989-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3232 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 551 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/077/05077684.pdf [firstpage_image] =>[orig_patent_app_number] => 437694 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/437694
System for accurately informing each of adapters of its packaged location Nov 16, 1989 Issued
07/435970 PROGRAMMABLE CACHE CONTROLLER Nov 12, 1989 Abandoned
07/434588 INTERFACE BETWEEN PROCESSOR AND SPECIAL INSTRUCTION PROCESSOR IN DIGITAL DATA PROCESSING SYSTEM Nov 12, 1989 Abandoned
07/435124 MICROCOMPUTER INTERFACE ARRANGEMENT Nov 12, 1989 Abandoned
Array ( [id] => 2927360 [patent_doc_number] => 05179661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Method and apparatus for serial data flow control' [patent_app_type] => 1 [patent_app_number] => 7/429065 [patent_app_country] => US [patent_app_date] => 1989-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3958 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179661.pdf [firstpage_image] =>[orig_patent_app_number] => 429065 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/429065
Method and apparatus for serial data flow control Oct 29, 1989 Issued
Array ( [id] => 2818331 [patent_doc_number] => 05148538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Translation look ahead based cache access' [patent_app_type] => 1 [patent_app_number] => 7/424496 [patent_app_country] => US [patent_app_date] => 1989-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 6447 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/148/05148538.pdf [firstpage_image] =>[orig_patent_app_number] => 424496 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/424496
Translation look ahead based cache access Oct 19, 1989 Issued
Array ( [id] => 2882458 [patent_doc_number] => 05163120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-10 [patent_title] => 'Second nearest-neighbor communication network for synchronous vector processor, systems and methods' [patent_app_type] => 1 [patent_app_number] => 7/421499 [patent_app_country] => US [patent_app_date] => 1989-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 73 [patent_no_of_words] => 32914 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 464 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/163/05163120.pdf [firstpage_image] =>[orig_patent_app_number] => 421499 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/421499
Second nearest-neighbor communication network for synchronous vector processor, systems and methods Oct 12, 1989 Issued
Array ( [id] => 2864070 [patent_doc_number] => 05134698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-28 [patent_title] => 'Data processing system having a storage controller for transferring an arbitrary amount of data at an arbitrary address boundary between storages' [patent_app_type] => 1 [patent_app_number] => 7/409764 [patent_app_country] => US [patent_app_date] => 1989-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4278 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/134/05134698.pdf [firstpage_image] =>[orig_patent_app_number] => 409764 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/409764
Data processing system having a storage controller for transferring an arbitrary amount of data at an arbitrary address boundary between storages Sep 19, 1989 Issued
07/408134 SYSTEM AND METHOD FOR REDUCING TIMING CHANNELS IN DIGITAL DATA PROCESSING SYSTEMS Sep 14, 1989 Abandoned
07/402705 PROCESSING CELL FOR FAULT TOLERANT ARRAYS Sep 4, 1989 Abandoned
Array ( [id] => 2955526 [patent_doc_number] => 05224213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-29 [patent_title] => 'Ping-pong data buffer for transferring data from one data bus to another data bus' [patent_app_type] => 1 [patent_app_number] => 7/402935 [patent_app_country] => US [patent_app_date] => 1989-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 11993 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 509 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/224/05224213.pdf [firstpage_image] =>[orig_patent_app_number] => 402935 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/402935
Ping-pong data buffer for transferring data from one data bus to another data bus Sep 4, 1989 Issued
07/400947 REMOTE MAINTENANCE AND ADMINISTRATION METHOD IN A SWITCHBOARD SYSTEM Aug 30, 1989 Abandoned
07/399449 A MICROPROCESSOR FOR EXECUTING INSTRUCTIONS THAT MAY BE DYNAMICALLY CHANGED Aug 27, 1989 Abandoned
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