Search

Eddie P. Chan

Examiner (ID: 4047)

Most Active Art Unit
2307
Art Unit(s)
2307, 2101, 2751, 2183, 2316
Total Applications
716
Issued Applications
479
Pending Applications
12
Abandoned Applications
224

Applications

Application numberTitle of the applicationFiling DateStatus
07/125463 REAL-TIME FAULT TOLERANT TRANSACTION PROCESSING SYSTEM Nov 24, 1987 Abandoned
07/114010 MICROPROCESSOR SYSTEM HAVING CACHE DIRECTORY AND CACHE MEMORY Oct 28, 1987 Abandoned
Array ( [id] => 2452403 [patent_doc_number] => 04751673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-06-14 [patent_title] => 'System for direct comparison and selective transmission of a plurality of discrete incoming data' [patent_app_type] => 1 [patent_app_number] => 7/117375 [patent_app_country] => US [patent_app_date] => 1987-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2990 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/751/04751673.pdf [firstpage_image] =>[orig_patent_app_number] => 117375 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/117375
System for direct comparison and selective transmission of a plurality of discrete incoming data Oct 27, 1987 Issued
Array ( [id] => 2623543 [patent_doc_number] => 04943914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-24 [patent_title] => 'Storage control system in which real address portion of TLB is on same chip as BAA' [patent_app_type] => 1 [patent_app_number] => 7/110425 [patent_app_country] => US [patent_app_date] => 1987-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4047 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/943/04943914.pdf [firstpage_image] =>[orig_patent_app_number] => 110425 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/110425
Storage control system in which real address portion of TLB is on same chip as BAA Oct 19, 1987 Issued
07/107634 DATA TRANSFER APPARATUS Oct 12, 1987 Abandoned
Array ( [id] => 2430162 [patent_doc_number] => 04780808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-10-25 [patent_title] => 'Control of cache buffer for memory subsystem' [patent_app_type] => 1 [patent_app_number] => 7/104565 [patent_app_country] => US [patent_app_date] => 1987-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 10735 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/780/04780808.pdf [firstpage_image] =>[orig_patent_app_number] => 104565 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/104565
Control of cache buffer for memory subsystem Oct 1, 1987 Issued
Array ( [id] => 1975719 [patent_doc_number] => 04354227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-10-12 [patent_title] => 'Fixed resource allocation method and apparatus for multiprocessor systems having complementarily phased cycles' [patent_app_type] => 1 [patent_app_number] => 6/095840 [patent_app_country] => US [patent_app_date] => 1979-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5058 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 492 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/354/04354227.pdf [firstpage_image] =>[orig_patent_app_number] => 095840 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/095840
Constant velocity joint cage and method for making same Sep 13, 1987 Issued
Array ( [id] => 1975719 [patent_doc_number] => 04354227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-10-12 [patent_title] => 'Fixed resource allocation method and apparatus for multiprocessor systems having complementarily phased cycles' [patent_app_type] => 1 [patent_app_number] => 6/095840 [patent_app_country] => US [patent_app_date] => 1979-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5058 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 492 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/354/04354227.pdf [firstpage_image] =>[orig_patent_app_number] => 095840 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/095840
Constant velocity joint cage and method for making same Sep 13, 1987 Issued
Array ( [id] => 1975719 [patent_doc_number] => 04354227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-10-12 [patent_title] => 'Fixed resource allocation method and apparatus for multiprocessor systems having complementarily phased cycles' [patent_app_type] => 1 [patent_app_number] => 6/095840 [patent_app_country] => US [patent_app_date] => 1979-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5058 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 492 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/354/04354227.pdf [firstpage_image] =>[orig_patent_app_number] => 095840 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/095840
Constant velocity joint cage and method for making same Sep 13, 1987 Issued
Array ( [id] => 1975719 [patent_doc_number] => 04354227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-10-12 [patent_title] => 'Fixed resource allocation method and apparatus for multiprocessor systems having complementarily phased cycles' [patent_app_type] => 1 [patent_app_number] => 6/095840 [patent_app_country] => US [patent_app_date] => 1979-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5058 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 492 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/354/04354227.pdf [firstpage_image] =>[orig_patent_app_number] => 095840 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/095840
Constant velocity joint cage and method for making same Sep 13, 1987 Issued
07/086868 A MICROPROCESSOR FOR EXECUTING INSTRUCTIONS THAT MAY BE DYNAMICALLY CHANGED Aug 18, 1987 Abandoned
Array ( [id] => 2573067 [patent_doc_number] => 04858117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-15 [patent_title] => 'Apparatus and method for preventing computer access by unauthorized personnel' [patent_app_type] => 1 [patent_app_number] => 7/083534 [patent_app_country] => US [patent_app_date] => 1987-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6223 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/858/04858117.pdf [firstpage_image] =>[orig_patent_app_number] => 083534 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/083534
Apparatus and method for preventing computer access by unauthorized personnel Aug 6, 1987 Issued
Array ( [id] => 2610873 [patent_doc_number] => 04931922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-05 [patent_title] => 'Method and apparatus for monitoring peripheral device communications' [patent_app_type] => 1 [patent_app_number] => 7/079218 [patent_app_country] => US [patent_app_date] => 1987-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 40 [patent_no_of_words] => 21630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/931/04931922.pdf [firstpage_image] =>[orig_patent_app_number] => 079218 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/079218
Method and apparatus for monitoring peripheral device communications Jul 28, 1987 Issued
07/079225 DIGITAL DATA PROCESSOR WITH FAULT-TOLERANT PERIPHERAL INTERFACE Jul 28, 1987 Abandoned
Array ( [id] => 2651370 [patent_doc_number] => 04939643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-03 [patent_title] => 'Fault tolerant digital data processor with improved bus protocol' [patent_app_type] => 1 [patent_app_number] => 7/079223 [patent_app_country] => US [patent_app_date] => 1987-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 40 [patent_no_of_words] => 21444 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/939/04939643.pdf [firstpage_image] =>[orig_patent_app_number] => 079223 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/079223
Fault tolerant digital data processor with improved bus protocol Jul 28, 1987 Issued
Array ( [id] => 2594288 [patent_doc_number] => 04926315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-15 [patent_title] => 'Digital data processor with fault tolerant peripheral bus communications' [patent_app_type] => 1 [patent_app_number] => 7/079297 [patent_app_country] => US [patent_app_date] => 1987-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 40 [patent_no_of_words] => 22384 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/926/04926315.pdf [firstpage_image] =>[orig_patent_app_number] => 079297 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/079297
Digital data processor with fault tolerant peripheral bus communications Jul 28, 1987 Issued
07/079295 DIGITAL DATA PROCESSOR WITH FAULT-TOLERANT INPUT/OUTPUT CONTROLLER Jul 28, 1987 Abandoned
07/076538 UNIVERSAL INPUT/OUTPUT DEVICE Jul 21, 1987 Abandoned
Array ( [id] => 2623455 [patent_doc_number] => 04943909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-24 [patent_title] => 'Computational origami' [patent_app_type] => 1 [patent_app_number] => 7/071105 [patent_app_country] => US [patent_app_date] => 1987-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 7010 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/943/04943909.pdf [firstpage_image] =>[orig_patent_app_number] => 071105 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/071105
Computational origami Jul 7, 1987 Issued
07/069436 APPARATUS AND METHOD FOR CONTROL OF ASYNCHRONOUS PROGRAM INTERRUPT EVENTS IN A DATA PROCESSING SYSTEM Jun 30, 1987 Abandoned
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