| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2493672
[patent_doc_number] => 04866608
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-09-12
[patent_title] => 'Microprocessor with improved execution of instructions'
[patent_app_type] => 1
[patent_app_number] => 6/926539
[patent_app_country] => US
[patent_app_date] => 1986-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3806
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/866/04866608.pdf
[firstpage_image] =>[orig_patent_app_number] => 926539
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/926539 | Microprocessor with improved execution of instructions | Nov 3, 1986 | Issued |
| 06/925344 | MULTIPLE DMA CONTROLLER CHIP SEQUENCER | Oct 30, 1986 | Abandoned |
Array
(
[id] => 2401740
[patent_doc_number] => 04769781
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-09-06
[patent_title] => 'IC device compatible with input signals in the formats for two-line and four-line type bus lines'
[patent_app_type] => 1
[patent_app_number] => 6/925374
[patent_app_country] => US
[patent_app_date] => 1986-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 4165
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/769/04769781.pdf
[firstpage_image] =>[orig_patent_app_number] => 925374
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/925374 | IC device compatible with input signals in the formats for two-line and four-line type bus lines | Oct 29, 1986 | Issued |
| 06/921151 | DIGITAL SIGNAL PROCESSOR | Oct 20, 1986 | Abandoned |
Array
(
[id] => 2417765
[patent_doc_number] => 04761734
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-08-02
[patent_title] => 'Data-processing apparatus provided with a finite-state machine to perform a program jump'
[patent_app_type] => 1
[patent_app_number] => 6/914049
[patent_app_country] => US
[patent_app_date] => 1986-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 5332
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 347
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/761/04761734.pdf
[firstpage_image] =>[orig_patent_app_number] => 914049
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/914049 | Data-processing apparatus provided with a finite-state machine to perform a program jump | Sep 30, 1986 | Issued |
Array
(
[id] => 2457535
[patent_doc_number] => 04758946
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-07-19
[patent_title] => 'Page mapping system'
[patent_app_type] => 1
[patent_app_number] => 6/912218
[patent_app_country] => US
[patent_app_date] => 1986-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 6013
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 368
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/758/04758946.pdf
[firstpage_image] =>[orig_patent_app_number] => 912218
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/912218 | Page mapping system | Sep 25, 1986 | Issued |
| 06/910461 | SEMICONDUCTOR DISK DEVICE | Sep 22, 1986 | Abandoned |
Array
(
[id] => 2389458
[patent_doc_number] => 04783730
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-11-08
[patent_title] => 'Input/output control technique utilizing multilevel memory structure for processor and I/O communication'
[patent_app_type] => 1
[patent_app_number] => 6/910006
[patent_app_country] => US
[patent_app_date] => 1986-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 19531
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 441
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/783/04783730.pdf
[firstpage_image] =>[orig_patent_app_number] => 910006
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/910006 | Input/output control technique utilizing multilevel memory structure for processor and I/O communication | Sep 18, 1986 | Issued |
| 06/907568 | MULTIPLE PROCESSOR COMPUTER SYSTEM | Sep 14, 1986 | Abandoned |
Array
(
[id] => 2453761
[patent_doc_number] => 04750177
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-06-07
[patent_title] => 'Digital data processor apparatus with pipelined fault tolerant bus protocol'
[patent_app_type] => 1
[patent_app_number] => 6/904827
[patent_app_country] => US
[patent_app_date] => 1986-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 22
[patent_no_of_words] => 33238
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/750/04750177.pdf
[firstpage_image] =>[orig_patent_app_number] => 904827
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/904827 | Digital data processor apparatus with pipelined fault tolerant bus protocol | Sep 7, 1986 | Issued |
Array
(
[id] => 2571573
[patent_doc_number] => 04849879
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-07-18
[patent_title] => 'Data processor performance advisor'
[patent_app_type] => 1
[patent_app_number] => 6/904093
[patent_app_country] => US
[patent_app_date] => 1986-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 33
[patent_no_of_words] => 21060
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 474
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/849/04849879.pdf
[firstpage_image] =>[orig_patent_app_number] => 904093
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/904093 | Data processor performance advisor | Sep 1, 1986 | Issued |
| 06/894841 | DATA PROCESSOR | Aug 7, 1986 | Abandoned |
| 06/889568 | MICROPROCESSOR INTERFACE DEVICE | Jul 24, 1986 | Abandoned |
| 06/888064 | DATA PROCESSING MACHINE | Jul 21, 1986 | Abandoned |
Array
(
[id] => 2428223
[patent_doc_number] => 04734849
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-03-29
[patent_title] => 'Information-processing system having a single chip arithmetic control unit with means for prefetching instructions'
[patent_app_type] => 1
[patent_app_number] => 6/886807
[patent_app_country] => US
[patent_app_date] => 1986-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 10927
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 377
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/734/04734849.pdf
[firstpage_image] =>[orig_patent_app_number] => 886807
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/886807 | Information-processing system having a single chip arithmetic control unit with means for prefetching instructions | Jul 15, 1986 | Issued |
Array
(
[id] => 2452408
[patent_doc_number] => 04740889
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-04-26
[patent_title] => 'Cache disable for a data processor'
[patent_app_type] => 1
[patent_app_number] => 6/885801
[patent_app_country] => US
[patent_app_date] => 1986-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3945
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/740/04740889.pdf
[firstpage_image] =>[orig_patent_app_number] => 885801
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/885801 | Cache disable for a data processor | Jul 13, 1986 | Issued |
Array
(
[id] => 2451459
[patent_doc_number] => 04722070
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-01-26
[patent_title] => 'Multiple oscillation switching circuit'
[patent_app_type] => 1
[patent_app_number] => 6/882019
[patent_app_country] => US
[patent_app_date] => 1986-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1709
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/722/04722070.pdf
[firstpage_image] =>[orig_patent_app_number] => 882019
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/882019 | Multiple oscillation switching circuit | Jul 2, 1986 | Issued |
Array
(
[id] => 2301674
[patent_doc_number] => 04697234
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-09-29
[patent_title] => 'Data processing module with serial test data paths'
[patent_app_type] => 1
[patent_app_number] => 6/880302
[patent_app_country] => US
[patent_app_date] => 1986-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2049
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/697/04697234.pdf
[firstpage_image] =>[orig_patent_app_number] => 880302
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/880302 | Data processing module with serial test data paths | Jun 29, 1986 | Issued |
Array
(
[id] => 2562139
[patent_doc_number] => 04803619
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-02-07
[patent_title] => 'Digital data processing system incorporating apparatus for resolving names'
[patent_app_type] => 1
[patent_app_number] => 6/877699
[patent_app_country] => US
[patent_app_date] => 1986-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2059
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 368
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/803/04803619.pdf
[firstpage_image] =>[orig_patent_app_number] => 877699
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/877699 | Digital data processing system incorporating apparatus for resolving names | Jun 19, 1986 | Issued |
| 06/875114 | METHOD AND APPARATUS FOR IMPLEMENTING A CONCURRENT LOGIC PROGRAM | Jun 16, 1986 | Abandoned |