
Eddie P. Chan
Examiner (ID: 4047)
| Most Active Art Unit | 2307 |
| Art Unit(s) | 2307, 2101, 2751, 2183, 2316 |
| Total Applications | 716 |
| Issued Applications | 479 |
| Pending Applications | 12 |
| Abandoned Applications | 224 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2422856
[patent_doc_number] => 04736317
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-04-05
[patent_title] => 'Microprogram-coupled multiple-microprocessor module with 32-bit byte width formed of 8-bit byte width microprocessors'
[patent_app_type] => 1
[patent_app_number] => 6/756048
[patent_app_country] => US
[patent_app_date] => 1985-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 13554
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 488
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/736/04736317.pdf
[firstpage_image] =>[orig_patent_app_number] => 756048
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/756048 | Microprogram-coupled multiple-microprocessor module with 32-bit byte width formed of 8-bit byte width microprocessors | Jul 16, 1985 | Issued |
Array
(
[id] => 2396944
[patent_doc_number] => 04794526
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-12-27
[patent_title] => 'Microcomputer with priority scheduling'
[patent_app_type] => 1
[patent_app_number] => 6/756993
[patent_app_country] => US
[patent_app_date] => 1985-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 49
[patent_no_of_words] => 24686
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 332
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/794/04794526.pdf
[firstpage_image] =>[orig_patent_app_number] => 756993
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/756993 | Microcomputer with priority scheduling | Jul 2, 1985 | Issued |
Array
(
[id] => 2557936
[patent_doc_number] => 04811277
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-03-07
[patent_title] => 'Communication interface'
[patent_app_type] => 1
[patent_app_number] => 6/756992
[patent_app_country] => US
[patent_app_date] => 1985-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 7411
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 390
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/811/04811277.pdf
[firstpage_image] =>[orig_patent_app_number] => 756992
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/756992 | Communication interface | Jul 2, 1985 | Issued |
Array
(
[id] => 2292115
[patent_doc_number] => 04587631
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-05-06
[patent_title] => 'Automatic text adjustment'
[patent_app_type] => 1
[patent_app_number] => 6/750978
[patent_app_country] => US
[patent_app_date] => 1985-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 3966
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 340
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/587/04587631.pdf
[firstpage_image] =>[orig_patent_app_number] => 750978
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/750978 | Automatic text adjustment | Jun 30, 1985 | Issued |
| 06/748409 | SELECTIVE OPERATION OF PROCESSING ELEMENTS IN A SINGLE INSTRUCTION, MULTIPLE DATA STREAM (SIMD) COMPUTER SYSTEM | Jun 23, 1985 | Abandoned |
Array
(
[id] => 2334636
[patent_doc_number] => 04672537
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-06-09
[patent_title] => 'Data error detection and device controller failure detection in an input/output system'
[patent_app_type] => 1
[patent_app_number] => 6/727614
[patent_app_country] => US
[patent_app_date] => 1985-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 42
[patent_no_of_words] => 42307
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/672/04672537.pdf
[firstpage_image] =>[orig_patent_app_number] => 727614
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/727614 | Data error detection and device controller failure detection in an input/output system | Apr 28, 1985 | Issued |
Array
(
[id] => 2461727
[patent_doc_number] => 04766567
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-08-23
[patent_title] => 'One-chip data processing device including low voltage detector'
[patent_app_type] => 1
[patent_app_number] => 6/722075
[patent_app_country] => US
[patent_app_date] => 1985-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 6587
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/766/04766567.pdf
[firstpage_image] =>[orig_patent_app_number] => 722075
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/722075 | One-chip data processing device including low voltage detector | Apr 10, 1985 | Issued |
Array
(
[id] => 2334608
[patent_doc_number] => 04672535
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-06-09
[patent_title] => 'Multiprocessor system'
[patent_app_type] => 1
[patent_app_number] => 6/713583
[patent_app_country] => US
[patent_app_date] => 1985-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 42
[patent_no_of_words] => 42920
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/672/04672535.pdf
[firstpage_image] =>[orig_patent_app_number] => 713583
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/713583 | Multiprocessor system | Mar 17, 1985 | Issued |
| 06/707617 | INFORMATION PROCESSOR EXECUTING INTERRUPTION PROGRAM WITHOUT SAVING CONTENTS OF PROGRAM COUNTER | Mar 3, 1985 | Abandoned |
Array
(
[id] => 2346148
[patent_doc_number] => 04713749
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-12-15
[patent_title] => 'Microprocessor with repeat instruction'
[patent_app_type] => 1
[patent_app_number] => 6/701829
[patent_app_country] => US
[patent_app_date] => 1985-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 66
[patent_no_of_words] => 41208
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 439
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/713/04713749.pdf
[firstpage_image] =>[orig_patent_app_number] => 701829
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/701829 | Microprocessor with repeat instruction | Feb 11, 1985 | Issued |
Array
(
[id] => 2346134
[patent_doc_number] => 04713748
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-12-15
[patent_title] => 'Microprocessor with block move instruction'
[patent_app_type] => 1
[patent_app_number] => 6/701827
[patent_app_country] => US
[patent_app_date] => 1985-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 66
[patent_no_of_words] => 41204
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 394
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/713/04713748.pdf
[firstpage_image] =>[orig_patent_app_number] => 701827
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/701827 | Microprocessor with block move instruction | Feb 11, 1985 | Issued |
Array
(
[id] => 2396778
[patent_doc_number] => 04773043
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-09-20
[patent_title] => 'ADCCP communication processor'
[patent_app_type] => 1
[patent_app_number] => 6/698725
[patent_app_country] => US
[patent_app_date] => 1985-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1980
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 296
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/773/04773043.pdf
[firstpage_image] =>[orig_patent_app_number] => 698725
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/698725 | ADCCP communication processor | Feb 5, 1985 | Issued |
Array
(
[id] => 2241782
[patent_doc_number] => 04597084
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-06-24
[patent_title] => 'Computer memory apparatus'
[patent_app_type] => 1
[patent_app_number] => 6/698257
[patent_app_country] => US
[patent_app_date] => 1985-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 22
[patent_no_of_words] => 33571
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/597/04597084.pdf
[firstpage_image] =>[orig_patent_app_number] => 698257
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/698257 | Computer memory apparatus | Feb 3, 1985 | Issued |
Array
(
[id] => 2133573
[patent_doc_number] => 04543629
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-09-24
[patent_title] => 'Apparatus for maximizing bus utilization'
[patent_app_type] => 1
[patent_app_number] => 6/690836
[patent_app_country] => US
[patent_app_date] => 1985-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6468
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 344
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/543/04543629.pdf
[firstpage_image] =>[orig_patent_app_number] => 690836
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/690836 | Apparatus for maximizing bus utilization | Jan 13, 1985 | Issued |
| 06/690478 | DATA COMPRESSION BY REMOVING REPETITION AND UNNECESSARY INFORMATION | Jan 9, 1985 | Abandoned |
Array
(
[id] => 2220792
[patent_doc_number] => 04615006
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-09-30
[patent_title] => 'Physical address developing unit'
[patent_app_type] => 1
[patent_app_number] => 6/682956
[patent_app_country] => US
[patent_app_date] => 1984-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3570
[patent_no_of_claims] => 5
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[patent_words_short_claim] => 429
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/615/04615006.pdf
[firstpage_image] =>[orig_patent_app_number] => 682956
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/682956 | Physical address developing unit | Dec 17, 1984 | Issued |
Array
(
[id] => 2362927
[patent_doc_number] => 04683466
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-07-28
[patent_title] => 'Multiple color generation on a display'
[patent_app_type] => 1
[patent_app_number] => 6/681539
[patent_app_country] => US
[patent_app_date] => 1984-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3558
[patent_no_of_claims] => 7
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[patent_words_short_claim] => 277
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/683/04683466.pdf
[firstpage_image] =>[orig_patent_app_number] => 681539
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/681539 | Multiple color generation on a display | Dec 13, 1984 | Issued |
Array
(
[id] => 2178770
[patent_doc_number] => 04556806
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-12-03
[patent_title] => 'Gate alterable output buffer'
[patent_app_type] => 1
[patent_app_number] => 6/673823
[patent_app_country] => US
[patent_app_date] => 1984-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3022
[patent_no_of_claims] => 10
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/556/04556806.pdf
[firstpage_image] =>[orig_patent_app_number] => 673823
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/673823 | Gate alterable output buffer | Nov 20, 1984 | Issued |
Array
(
[id] => 2392518
[patent_doc_number] => 04707781
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-11-17
[patent_title] => 'Shared memory computer method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 6/673159
[patent_app_country] => US
[patent_app_date] => 1984-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 20
[patent_no_of_words] => 9546
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/707/04707781.pdf
[firstpage_image] =>[orig_patent_app_number] => 673159
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/673159 | Shared memory computer method and apparatus | Nov 18, 1984 | Issued |
Array
(
[id] => 2358557
[patent_doc_number] => 04654781
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-03-31
[patent_title] => 'Byte addressable memory for variable length instructions and data'
[patent_app_type] => 1
[patent_app_number] => 6/665510
[patent_app_country] => US
[patent_app_date] => 1984-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 4471
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/654/04654781.pdf
[firstpage_image] =>[orig_patent_app_number] => 665510
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/665510 | Byte addressable memory for variable length instructions and data | Oct 29, 1984 | Issued |