Search

Eddie P. Chan

Examiner (ID: 4047)

Most Active Art Unit
2307
Art Unit(s)
2307, 2101, 2751, 2183, 2316
Total Applications
716
Issued Applications
479
Pending Applications
12
Abandoned Applications
224

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2021763 [patent_doc_number] => 04400794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-08-23 [patent_title] => 'Memory mapping unit' [patent_app_type] => 1 [patent_app_number] => 6/322118 [patent_app_country] => US [patent_app_date] => 1981-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1779 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/400/04400794.pdf [firstpage_image] =>[orig_patent_app_number] => 322118 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/322118
Memory mapping unit Nov 16, 1981 Issued
Array ( [id] => 2115502 [patent_doc_number] => 04451881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-05-29 [patent_title] => 'Data processing system bus for multiple independent users' [patent_app_type] => 1 [patent_app_number] => 6/317824 [patent_app_country] => US [patent_app_date] => 1981-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6702 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 443 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/451/04451881.pdf [firstpage_image] =>[orig_patent_app_number] => 317824 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/317824
Data processing system bus for multiple independent users Nov 2, 1981 Issued
Array ( [id] => 2125124 [patent_doc_number] => 04481583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-11-06 [patent_title] => 'Method for distributing resources in a time-shared system' [patent_app_type] => 1 [patent_app_number] => 6/316878 [patent_app_country] => US [patent_app_date] => 1981-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3623 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/481/04481583.pdf [firstpage_image] =>[orig_patent_app_number] => 316878 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/316878
Method for distributing resources in a time-shared system Oct 29, 1981 Issued
Array ( [id] => 2328465 [patent_doc_number] => 04670857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-06-02 [patent_title] => 'Cartridge-controlled system whose use is limited to authorized cartridges' [patent_app_type] => 1 [patent_app_number] => 6/315204 [patent_app_country] => US [patent_app_date] => 1981-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3617 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/670/04670857.pdf [firstpage_image] =>[orig_patent_app_number] => 315204 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/315204
Cartridge-controlled system whose use is limited to authorized cartridges Oct 25, 1981 Issued
06/308006 BYTE ADDRESSABLE MEMORY FOR VARIABLE LENGTH INSTRUCTIONS AND DATA Oct 1, 1981 Abandoned
Array ( [id] => 2089857 [patent_doc_number] => 04438490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-03-20 [patent_title] => 'Clock control of a central processing unit from a monitor interface unit' [patent_app_type] => 1 [patent_app_number] => 6/307564 [patent_app_country] => US [patent_app_date] => 1981-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 9402 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 400 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/438/04438490.pdf [firstpage_image] =>[orig_patent_app_number] => 307564 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/307564
Clock control of a central processing unit from a monitor interface unit Sep 30, 1981 Issued
06/307808 DIGITAL DOCUMENT SCANNING SYSTEM Sep 30, 1981 Abandoned
06/307502 COMPUTER MEMORY APPARATUS Sep 30, 1981 Abandoned
06/307436 DIGITAL DATA PROCESSOR WITH FAULT TOLERANT BUS PROTOCOL Sep 30, 1981 Abandoned
Array ( [id] => 2110935 [patent_doc_number] => 04472789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-09-18 [patent_title] => 'Vital timer' [patent_app_type] => 1 [patent_app_number] => 6/304093 [patent_app_country] => US [patent_app_date] => 1981-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 7645 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/472/04472789.pdf [firstpage_image] =>[orig_patent_app_number] => 304093 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/304093
Vital timer Sep 20, 1981 Issued
Array ( [id] => 2084956 [patent_doc_number] => 04450365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-05-22 [patent_title] => 'Digital logic buffer for converting single polarity analog signals to dual polarity analog signals' [patent_app_type] => 1 [patent_app_number] => 6/302318 [patent_app_country] => US [patent_app_date] => 1981-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5777 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/450/04450365.pdf [firstpage_image] =>[orig_patent_app_number] => 302318 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/302318
Digital logic buffer for converting single polarity analog signals to dual polarity analog signals Sep 13, 1981 Issued
Array ( [id] => 2041706 [patent_doc_number] => 04414627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-11-08 [patent_title] => 'Main memory control system' [patent_app_type] => 1 [patent_app_number] => 6/296978 [patent_app_country] => US [patent_app_date] => 1981-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3062 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 657 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/414/04414627.pdf [firstpage_image] =>[orig_patent_app_number] => 296978 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/296978
Main memory control system Aug 26, 1981 Issued
Array ( [id] => 2098594 [patent_doc_number] => 04456956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-06-26 [patent_title] => 'Method and apparatus for controlling access of a network transmission bus between a plurality of spaced apart computer stations' [patent_app_type] => 1 [patent_app_number] => 6/295537 [patent_app_country] => US [patent_app_date] => 1981-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 63 [patent_no_of_words] => 25128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/456/04456956.pdf [firstpage_image] =>[orig_patent_app_number] => 295537 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/295537
Method and apparatus for controlling access of a network transmission bus between a plurality of spaced apart computer stations Aug 23, 1981 Issued
Array ( [id] => 2063828 [patent_doc_number] => 04409671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-10-11 [patent_title] => 'Data processor having single clock pin' [patent_app_type] => 1 [patent_app_number] => 6/295912 [patent_app_country] => US [patent_app_date] => 1981-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1449 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/409/04409671.pdf [firstpage_image] =>[orig_patent_app_number] => 295912 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/295912
Data processor having single clock pin Aug 23, 1981 Issued
Array ( [id] => 2113088 [patent_doc_number] => 04467414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-08-21 [patent_title] => 'Cashe memory arrangement comprising a cashe buffer in combination with a pair of cache memories' [patent_app_type] => 1 [patent_app_number] => 6/294121 [patent_app_country] => US [patent_app_date] => 1981-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8238 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 654 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/467/04467414.pdf [firstpage_image] =>[orig_patent_app_number] => 294121 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/294121
Cashe memory arrangement comprising a cashe buffer in combination with a pair of cache memories Aug 18, 1981 Issued
Array ( [id] => 2202809 [patent_doc_number] => 04495564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-01-22 [patent_title] => 'Multi sub-channel adapter with single status/address register' [patent_app_type] => 1 [patent_app_number] => 6/291741 [patent_app_country] => US [patent_app_date] => 1981-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5187 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/495/04495564.pdf [firstpage_image] =>[orig_patent_app_number] => 291741 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/291741
Multi sub-channel adapter with single status/address register Aug 9, 1981 Issued
Array ( [id] => 2072277 [patent_doc_number] => 04430701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-02-07 [patent_title] => 'Method and apparatus for a hierarchical paging storage system' [patent_app_type] => 1 [patent_app_number] => 6/289631 [patent_app_country] => US [patent_app_date] => 1981-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 11187 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/430/04430701.pdf [firstpage_image] =>[orig_patent_app_number] => 289631 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/289631
Method and apparatus for a hierarchical paging storage system Aug 2, 1981 Issued
06/283837 VECTOR DATA PROCESSOR Jul 15, 1981 Abandoned
06/274363 AUTOMATIC TEXT ADJUSTMENT Jun 15, 1981 Abandoned
Array ( [id] => 2203349 [patent_doc_number] => 04503490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-03-05 [patent_title] => 'Distributed timing system' [patent_app_type] => 1 [patent_app_number] => 6/272300 [patent_app_country] => US [patent_app_date] => 1981-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5783 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/503/04503490.pdf [firstpage_image] =>[orig_patent_app_number] => 272300 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/272300
Distributed timing system Jun 9, 1981 Issued
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