Search

Edgar X. Guerra-erazo

Examiner (ID: 13854, Phone: (571)270-3708 , Office: P/2659 )

Most Active Art Unit
2659
Art Unit(s)
2626, 2659, 2656, 3649
Total Applications
951
Issued Applications
795
Pending Applications
53
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15369281 [patent_doc_number] => 20200020405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/579964 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 568 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16579964 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/579964
Nonvolatile semiconductor memory device Sep 23, 2019 Issued
Array ( [id] => 15351779 [patent_doc_number] => 20200013781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor [patent_app_type] => utility [patent_app_number] => 16/574069 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16574069 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/574069
Method of maintaining the state of semiconductor memory having electrically floating body transistor Sep 16, 2019 Issued
Array ( [id] => 15351777 [patent_doc_number] => 20200013780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making [patent_app_type] => utility [patent_app_number] => 16/573302 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573302 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/573302
Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making Sep 16, 2019 Issued
Array ( [id] => 15532057 [patent_doc_number] => 20200058334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => WRITE CYCLE EXECUTION BASED ON DATA COMPARISON [patent_app_type] => utility [patent_app_number] => 16/572278 [patent_app_country] => US [patent_app_date] => 2019-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16572278 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/572278
Write cycle execution based on data comparison Sep 15, 2019 Issued
Array ( [id] => 16835281 [patent_doc_number] => 11011541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Semiconductor memory device in which memory cells are three-dimensionally arrange [patent_app_type] => utility [patent_app_number] => 16/559389 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15072 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559389 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559389
Semiconductor memory device in which memory cells are three-dimensionally arrange Sep 2, 2019 Issued
Array ( [id] => 15597063 [patent_doc_number] => 20200075066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/556381 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16556381 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/556381
Memory device including noise-suppressing mechanism Aug 29, 2019 Issued
Array ( [id] => 16707439 [patent_doc_number] => 10957381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-23 [patent_title] => Metadata grouping for un-map techniques [patent_app_type] => utility [patent_app_number] => 16/553358 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10570 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553358 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/553358
Metadata grouping for un-map techniques Aug 27, 2019 Issued
Array ( [id] => 15259659 [patent_doc_number] => 20190378563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => METHOD AND APPARATUS FOR PRECHARGE AND REFRESH CONTROL [patent_app_type] => utility [patent_app_number] => 16/548605 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548605 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/548605
Method and apparatus for precharge and refresh control Aug 21, 2019 Issued
Array ( [id] => 15532073 [patent_doc_number] => 20200058342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => ACCESS SCHEMES FOR SECTION-BASED DATA PROTECTION IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/536078 [patent_app_country] => US [patent_app_date] => 2019-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16536078 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/536078
Access schemes for section-based data protection in a memory device Aug 7, 2019 Issued
Array ( [id] => 15388381 [patent_doc_number] => 10535385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Semiconductor integrated circuit and semiconductor device [patent_app_type] => utility [patent_app_number] => 16/523373 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3907 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523373 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523373
Semiconductor integrated circuit and semiconductor device Jul 25, 2019 Issued
Array ( [id] => 15122961 [patent_doc_number] => 20190348114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => TAILORING CURRENT MAGNITUDE AND DURATION DURING A PROGRAMMING PULSE FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/520213 [patent_app_country] => US [patent_app_date] => 2019-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16520213 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/520213
Tailoring current magnitude and duration during a programming pulse for a memory device Jul 22, 2019 Issued
Array ( [id] => 15153883 [patent_doc_number] => 20190355419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => MEMORY CELLS, MEMORY CELL ARRAYS, METHODS OF USING AND METHODS OF MAKING [patent_app_type] => utility [patent_app_number] => 16/519515 [patent_app_country] => US [patent_app_date] => 2019-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16519515 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/519515
Memory cells, memory cell arrays, methods of using and methods of making Jul 22, 2019 Issued
Array ( [id] => 15732899 [patent_doc_number] => 10614882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Access signal adjustment circuits and methods for memory cells in a cross-point array [patent_app_type] => utility [patent_app_number] => 16/511205 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511205 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/511205
Access signal adjustment circuits and methods for memory cells in a cross-point array Jul 14, 2019 Issued
Array ( [id] => 15518899 [patent_doc_number] => 10566043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Multi-level storage in ferroelectric memory [patent_app_type] => utility [patent_app_number] => 16/504889 [patent_app_country] => US [patent_app_date] => 2019-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 22543 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16504889 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/504889
Multi-level storage in ferroelectric memory Jul 7, 2019 Issued
Array ( [id] => 14999671 [patent_doc_number] => 20190318793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => DYNAMIC FUSE SENSING AND LATCH CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/452747 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16452747 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/452747
Dynamic fuse sensing and latch circuit Jun 25, 2019 Issued
Array ( [id] => 15857385 [patent_doc_number] => 10643991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Apparatuses and memory devices including control logic levels, and related electronic systems [patent_app_type] => utility [patent_app_number] => 16/443628 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11284 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443628 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/443628
Apparatuses and memory devices including control logic levels, and related electronic systems Jun 16, 2019 Issued
Array ( [id] => 15077231 [patent_doc_number] => 10468110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Semiconductor device and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/443294 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 10929 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443294 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/443294
Semiconductor device and operating method thereof Jun 16, 2019 Issued
Array ( [id] => 15077237 [patent_doc_number] => 10468113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/441962 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 14469 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441962 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441962
Memory device and operating method thereof Jun 13, 2019 Issued
Array ( [id] => 15199883 [patent_doc_number] => 10497443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating [patent_app_type] => utility [patent_app_number] => 16/441396 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 391 [patent_figures_cnt] => 581 [patent_no_of_words] => 128526 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441396 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441396
Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating Jun 13, 2019 Issued
Array ( [id] => 15375365 [patent_doc_number] => 10529408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Memory controller for strobe-based memory systems [patent_app_type] => utility [patent_app_number] => 16/435308 [patent_app_country] => US [patent_app_date] => 2019-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7368 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435308 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/435308
Memory controller for strobe-based memory systems Jun 6, 2019 Issued
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