Search

Edgar X. Guerra-erazo

Examiner (ID: 13854, Phone: (571)270-3708 , Office: P/2659 )

Most Active Art Unit
2659
Art Unit(s)
2626, 2659, 2656, 3649
Total Applications
951
Issued Applications
795
Pending Applications
53
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17948991 [patent_doc_number] => 20220336010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => PRECISION TUNING OF A PAGE OR WORD OF NON-VOLATILE MEMORY CELLS IN AN ANALOG NEURAL MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/856839 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856839 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856839
Precision tuning of a page or word of non-volatile memory cells in an analog neural memory system Jun 30, 2022 Issued
Array ( [id] => 17932996 [patent_doc_number] => 20220328122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => MEMORY CHIP HAVING ON-DIE MIRRORING FUNCTION AND METHOD FOR TESTING THE SAME [patent_app_type] => utility [patent_app_number] => 17/851255 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851255 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851255
Memory chip having on-die mirroring function and method for testing the same Jun 27, 2022 Issued
Array ( [id] => 18967246 [patent_doc_number] => 11901024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Method and device for testing memory chip [patent_app_type] => utility [patent_app_number] => 17/851656 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851656 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851656
Method and device for testing memory chip Jun 27, 2022 Issued
Array ( [id] => 18192564 [patent_doc_number] => 20230046083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => MEMORY DEVICE USING SEMICONDUCTOR ELEMENT [patent_app_type] => utility [patent_app_number] => 17/844927 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844927 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/844927
Memory device using semiconductor element Jun 20, 2022 Issued
Array ( [id] => 19123398 [patent_doc_number] => 11967392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Method and apparatus for testing failure of memory, storage medium, and electronic device [patent_app_type] => utility [patent_app_number] => 17/841673 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8275 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841673
Method and apparatus for testing failure of memory, storage medium, and electronic device Jun 15, 2022 Issued
Array ( [id] => 18593141 [patent_doc_number] => 11742050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Error detection [patent_app_type] => utility [patent_app_number] => 17/839168 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 9657 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17839168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/839168
Error detection Jun 12, 2022 Issued
Array ( [id] => 18122668 [patent_doc_number] => 20230008272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => CIRCUIT AND METHOD TO DETECT WORD-LINE LEAKAGE AND PROCESS DEFECTS IN NON-VOLATILE MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/837377 [patent_app_country] => US [patent_app_date] => 2022-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17837377 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/837377
Circuit and method to detect word-line leakage and process defects in non-volatile memory array Jun 9, 2022 Issued
Array ( [id] => 19062892 [patent_doc_number] => 11942137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Memory controller and memory system including the same [patent_app_type] => utility [patent_app_number] => 17/829669 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 14851 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829669 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/829669
Memory controller and memory system including the same May 31, 2022 Issued
Array ( [id] => 18507358 [patent_doc_number] => 11705182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Electronic device for controlling command input [patent_app_type] => utility [patent_app_number] => 17/830091 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7370 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17830091 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/830091
Electronic device for controlling command input May 31, 2022 Issued
Array ( [id] => 18848507 [patent_doc_number] => 20230410911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => BALANCING PEAK POWER WITH PROGRAMMING SPEED IN NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/825321 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/825321
Balancing peak power with programming speed in non-volatile memory May 25, 2022 Issued
Array ( [id] => 18645490 [patent_doc_number] => 11769568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Method for LUT-free memory repair [patent_app_type] => utility [patent_app_number] => 17/751914 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 50 [patent_no_of_words] => 17740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751914 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751914
Method for LUT-free memory repair May 23, 2022 Issued
Array ( [id] => 18346797 [patent_doc_number] => 20230134907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/750642 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750642 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750642
Nonvolatile memory device with configuration to apply adjustable voltage to pass transistor gate May 22, 2022 Issued
Array ( [id] => 17963411 [patent_doc_number] => 20220343992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => COMMAND/ADDRESS CHANNEL ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 17/746674 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746674 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746674
Command/address channel error detection May 16, 2022 Issued
Array ( [id] => 17833398 [patent_doc_number] => 20220270702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => ERROR RECOVERY OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/743989 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743989 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743989
Error recovery operations May 12, 2022 Issued
Array ( [id] => 17810615 [patent_doc_number] => 20220262450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, MEMORY SYSTEM AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/739288 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739288 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739288
Semiconductor memory device, controller, memory system and method of operating the same May 8, 2022 Issued
Array ( [id] => 17795294 [patent_doc_number] => 20220254386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => SENSING AMPLIFIER, METHOD AND CONTROLLER FOR SENSING MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/731248 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731248
Sensing amplifier, method and controller for sensing memory cell Apr 26, 2022 Issued
Array ( [id] => 17779865 [patent_doc_number] => 20220246215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS [patent_app_type] => utility [patent_app_number] => 17/726059 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726059 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726059
Memory devices having source lines directly coupled to body regions and methods Apr 20, 2022 Issued
Array ( [id] => 17917170 [patent_doc_number] => 20220319566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SEMICONDUCTOR ELEMENT MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/713813 [patent_app_country] => US [patent_app_date] => 2022-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 477 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17713813 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/713813
Semiconductor element memory device Apr 4, 2022 Issued
Array ( [id] => 18250952 [patent_doc_number] => 20230077991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => DATA PROCESSING CIRCUIT AND FAULT MITIGATING METHOD [patent_app_type] => utility [patent_app_number] => 17/705415 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705415
Data processing circuit and fault mitigating method Mar 27, 2022 Issued
Array ( [id] => 18507350 [patent_doc_number] => 11705174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Integrated circuit with asymmetric arrangements of memory arrays [patent_app_type] => utility [patent_app_number] => 17/704644 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 14569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704644 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/704644
Integrated circuit with asymmetric arrangements of memory arrays Mar 24, 2022 Issued
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