Search

Edgar X. Guerra-erazo

Examiner (ID: 13854, Phone: (571)270-3708 , Office: P/2659 )

Most Active Art Unit
2659
Art Unit(s)
2626, 2659, 2656, 3649
Total Applications
951
Issued Applications
795
Pending Applications
53
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16438973 [patent_doc_number] => 20200356299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/936871 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936871
Memory system including a memory controller Jul 22, 2020 Issued
Array ( [id] => 17543902 [patent_doc_number] => 11309034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Memory cell arrangement and methods thereof [patent_app_type] => utility [patent_app_number] => 16/929685 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 26614 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929685 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/929685
Memory cell arrangement and methods thereof Jul 14, 2020 Issued
Array ( [id] => 17730539 [patent_doc_number] => 11386936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Memory device, sensing amplifier, and method for sensing memory cell [patent_app_type] => utility [patent_app_number] => 16/925295 [patent_app_country] => US [patent_app_date] => 2020-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7671 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925295 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/925295
Memory device, sensing amplifier, and method for sensing memory cell Jul 8, 2020 Issued
Array ( [id] => 16402081 [patent_doc_number] => 20200342939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => MEMORY CELLS, MEMORY CELL ARRAYS, METHODS OF USING AND METHODS OF MAKING [patent_app_type] => utility [patent_app_number] => 16/923934 [patent_app_country] => US [patent_app_date] => 2020-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16923934 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/923934
Memory cells, memory cell arrays, methods of using and methods of making Jul 7, 2020 Issued
Array ( [id] => 16394562 [patent_doc_number] => 20200335503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor [patent_app_type] => utility [patent_app_number] => 16/922282 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17549 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922282 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/922282
Method of maintaining the state of semiconductor memory having electrically floating body transistor Jul 6, 2020 Issued
Array ( [id] => 16578451 [patent_doc_number] => 20210012852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND ERROR NOTIFICATION METHOD [patent_app_type] => utility [patent_app_number] => 16/921255 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921255 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921255
Semiconductor memory device, memory controller, and error notification method Jul 5, 2020 Issued
Array ( [id] => 17339210 [patent_doc_number] => 20220005541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => MEMORY DEVICE TESTING, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/919922 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16919922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/919922
Memory device testing, and associated methods, devices, and systems Jul 1, 2020 Issued
Array ( [id] => 17410024 [patent_doc_number] => 11250920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Loop-dependent switching between program-verify techniques [patent_app_type] => utility [patent_app_number] => 16/916367 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 19414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916367 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916367
Loop-dependent switching between program-verify techniques Jun 29, 2020 Issued
Array ( [id] => 17332241 [patent_doc_number] => 11222709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Memory module with reduced ECC overhead and memory system [patent_app_type] => utility [patent_app_number] => 16/916463 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 9485 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916463 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916463
Memory module with reduced ECC overhead and memory system Jun 29, 2020 Issued
Array ( [id] => 16348189 [patent_doc_number] => 20200312840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => DEVICES, MEMORY DEVICES, AND METHODS OF FORMING DEVICES [patent_app_type] => utility [patent_app_number] => 16/902752 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902752 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/902752
Devices, memory devices, and methods of forming devices Jun 15, 2020 Issued
Array ( [id] => 16958901 [patent_doc_number] => 11062778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Nonvolatile semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/896644 [patent_app_country] => US [patent_app_date] => 2020-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 42 [patent_no_of_words] => 10692 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16896644 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/896644
Nonvolatile semiconductor memory device Jun 8, 2020 Issued
Array ( [id] => 17224491 [patent_doc_number] => 11177001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => 3D NAND flash and operation method thereof [patent_app_type] => utility [patent_app_number] => 16/888871 [patent_app_country] => US [patent_app_date] => 2020-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2471 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16888871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/888871
3D NAND flash and operation method thereof May 31, 2020 Issued
Array ( [id] => 17210495 [patent_doc_number] => 11170870 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-09 [patent_title] => On-chip-copy for integrated memory assembly [patent_app_type] => utility [patent_app_number] => 16/886685 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 42 [patent_no_of_words] => 26477 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886685 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886685
On-chip-copy for integrated memory assembly May 27, 2020 Issued
Array ( [id] => 16888646 [patent_doc_number] => 20210174843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/883410 [patent_app_country] => US [patent_app_date] => 2020-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/883410
Memory device and method of operating the same May 25, 2020 Issued
Array ( [id] => 16707432 [patent_doc_number] => 10957374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Memory cells and arrays of memory cells [patent_app_type] => utility [patent_app_number] => 16/878882 [patent_app_country] => US [patent_app_date] => 2020-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6166 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878882 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878882
Memory cells and arrays of memory cells May 19, 2020 Issued
Array ( [id] => 17380930 [patent_doc_number] => 11238952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Memory system, memory controller, and method of operating memory system [patent_app_type] => utility [patent_app_number] => 16/875358 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13272 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16875358 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/875358
Memory system, memory controller, and method of operating memory system May 14, 2020 Issued
Array ( [id] => 16272018 [patent_doc_number] => 20200273506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => WRITE CYCLE EXECUTION BASED ON DATA COMPARISON [patent_app_type] => utility [patent_app_number] => 16/872990 [patent_app_country] => US [patent_app_date] => 2020-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16872990 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/872990
Write cycle execution based on data comparison May 11, 2020 Issued
Array ( [id] => 16865649 [patent_doc_number] => 11024401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-01 [patent_title] => Compute an optimized read voltage [patent_app_type] => utility [patent_app_number] => 16/869495 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 12110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16869495 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/869495
Compute an optimized read voltage May 6, 2020 Issued
Array ( [id] => 16752280 [patent_doc_number] => 20210104292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => MEMORY CHIP HAVING ON-DIE MIRRORING FUNCTION AND METHOD FOR TESTING THE SAME [patent_app_type] => utility [patent_app_number] => 16/867631 [patent_app_country] => US [patent_app_date] => 2020-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16867631 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/867631
Memory chip having on-die mirroring function and method for testing the same May 5, 2020 Issued
Array ( [id] => 17971111 [patent_doc_number] => 11488658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Write assist scheme with bitline [patent_app_type] => utility [patent_app_number] => 16/862238 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7781 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862238 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/862238
Write assist scheme with bitline Apr 28, 2020 Issued
Menu