
Edgardo Ortiz
Examiner (ID: 7554)
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815 |
| Total Applications | 306 |
| Issued Applications | 269 |
| Pending Applications | 3 |
| Abandoned Applications | 34 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18178030
[patent_doc_number] => 20230038759
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-09
[patent_title] => FERROELECTRIC MEMORY STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/403871
[patent_app_country] => US
[patent_app_date] => 2021-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5690
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403871
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/403871 | Ferroelectric memory structure with different ferroelectric capacitors | Aug 15, 2021 | Issued |
Array
(
[id] => 17765187
[patent_doc_number] => 20220238801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-28
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/400912
[patent_app_country] => US
[patent_app_date] => 2021-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8995
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400912
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/400912 | Semiconductor memory device with a phase change layer and particular heater material | Aug 11, 2021 | Issued |
Array
(
[id] => 17246815
[patent_doc_number] => 20210366560
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-25
[patent_title] => IMPLEMENTING LOGIC FUNCTION AND GENERATING ANALOG SIGNALS USING NOR MEMORY STRINGS
[patent_app_type] => utility
[patent_app_number] => 17/394733
[patent_app_country] => US
[patent_app_date] => 2021-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 34274
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17394733
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/394733 | Implementing logic function and generating analog signals using NOR memory strings | Aug 4, 2021 | Issued |
Array
(
[id] => 18180254
[patent_doc_number] => 20230040983
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-09
[patent_title] => SPIKE-TIMING-DEPENDENT PLASTICITY USING INVERSE RESISTIVITY PHASE-CHANGE MATERIAL
[patent_app_type] => utility
[patent_app_number] => 17/394544
[patent_app_country] => US
[patent_app_date] => 2021-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10615
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17394544
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/394544 | SPIKE-TIMING-DEPENDENT PLASTICITY USING INVERSE RESISTIVITY PHASE-CHANGE MATERIAL | Aug 4, 2021 | Pending |
Array
(
[id] => 18607868
[patent_doc_number] => 11749344
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-05
[patent_title] => Three-dimensional vertical nor flash thin-film transistor strings
[patent_app_type] => utility
[patent_app_number] => 17/394249
[patent_app_country] => US
[patent_app_date] => 2021-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 21
[patent_no_of_words] => 16894
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17394249
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/394249 | Three-dimensional vertical nor flash thin-film transistor strings | Aug 3, 2021 | Issued |
Array
(
[id] => 17247403
[patent_doc_number] => 20210367148
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-25
[patent_title] => PHASE CHANGE MEMORY WITH CONDUCTIVE BRIDGE FILAMENT
[patent_app_type] => utility
[patent_app_number] => 17/393554
[patent_app_country] => US
[patent_app_date] => 2021-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5744
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393554
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/393554 | Phase change memory with conductive bridge filament | Aug 3, 2021 | Issued |
Array
(
[id] => 18841557
[patent_doc_number] => 11849655
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Semiconductor memory devices with electrically isolated stacked bit lines and methods of manufacture
[patent_app_type] => utility
[patent_app_number] => 17/383726
[patent_app_country] => US
[patent_app_date] => 2021-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 67
[patent_no_of_words] => 13213
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17383726
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/383726 | Semiconductor memory devices with electrically isolated stacked bit lines and methods of manufacture | Jul 22, 2021 | Issued |
Array
(
[id] => 17316835
[patent_doc_number] => 20210405884
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => HYBRID MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/374359
[patent_app_country] => US
[patent_app_date] => 2021-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16040
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17374359
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/374359 | Hybrid memory device using different types of capacitors | Jul 12, 2021 | Issued |
Array
(
[id] => 17993512
[patent_doc_number] => 20220359549
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => FERROEOLECTRIC MEMORIES
[patent_app_type] => utility
[patent_app_number] => 17/368686
[patent_app_country] => US
[patent_app_date] => 2021-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8190
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368686
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/368686 | Ferroeolectric memories with ferroelectric composite layer | Jul 5, 2021 | Issued |
Array
(
[id] => 17431906
[patent_doc_number] => 20220059615
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-24
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/364378
[patent_app_country] => US
[patent_app_date] => 2021-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12560
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364378
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/364378 | Semiconductor memory device with selection patterns, storage patterns, and a gap fill layer and method for fabricating the same | Jun 29, 2021 | Issued |
Array
(
[id] => 17144961
[patent_doc_number] => 20210312974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-07
[patent_title] => SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/353267
[patent_app_country] => US
[patent_app_date] => 2021-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 34302
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353267
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/353267 | Semiconductor devices | Jun 20, 2021 | Issued |
Array
(
[id] => 18081388
[patent_doc_number] => 20220407000
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-22
[patent_title] => MEMORY WITH LAMINATED CELL
[patent_app_type] => utility
[patent_app_number] => 17/349359
[patent_app_country] => US
[patent_app_date] => 2021-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6163
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17349359
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/349359 | MEMORY WITH LAMINATED CELL | Jun 15, 2021 | Abandoned |
Array
(
[id] => 18068405
[patent_doc_number] => 20220399493
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-15
[patent_title] => PHASE CHANGE MEMORY CELL WITH AN AIRGAP TO ALLOW FOR THE EXPANSION AND RESTRICTION OF THE PCM MATERIAL
[patent_app_type] => utility
[patent_app_number] => 17/303836
[patent_app_country] => US
[patent_app_date] => 2021-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8523
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17303836
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/303836 | Phase change memory cell with an airgap to allow for the expansion and restriction of the PCM material | Jun 8, 2021 | Issued |
Array
(
[id] => 18969520
[patent_doc_number] => 11903333
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-13
[patent_title] => Sidewall structures for memory cells in vertical structures
[patent_app_type] => utility
[patent_app_number] => 17/332654
[patent_app_country] => US
[patent_app_date] => 2021-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 25819
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332654
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/332654 | Sidewall structures for memory cells in vertical structures | May 26, 2021 | Issued |
Array
(
[id] => 18783945
[patent_doc_number] => 11825754
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-21
[patent_title] => Memory cells with sidewall and bulk regions in planar structures
[patent_app_type] => utility
[patent_app_number] => 17/332691
[patent_app_country] => US
[patent_app_date] => 2021-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 25604
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332691
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/332691 | Memory cells with sidewall and bulk regions in planar structures | May 26, 2021 | Issued |
Array
(
[id] => 18859264
[patent_doc_number] => 11856876
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-26
[patent_title] => Semiconductor devices with a double sided word line structure and methods of manufacture
[patent_app_type] => utility
[patent_app_number] => 17/332135
[patent_app_country] => US
[patent_app_date] => 2021-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 39
[patent_no_of_words] => 8197
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332135
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/332135 | Semiconductor devices with a double sided word line structure and methods of manufacture | May 26, 2021 | Issued |
Array
(
[id] => 18595245
[patent_doc_number] => 11744167
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-29
[patent_title] => Semiconductor apparatus including a phase change material layer having a first and a second chalcogen layer
[patent_app_type] => utility
[patent_app_number] => 17/330950
[patent_app_country] => US
[patent_app_date] => 2021-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 8522
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330950
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/330950 | Semiconductor apparatus including a phase change material layer having a first and a second chalcogen layer | May 25, 2021 | Issued |
Array
(
[id] => 17084002
[patent_doc_number] => 20210279008
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-09
[patent_title] => APPARATUSES AND METHODS FOR IN-MEMORY OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 17/328522
[patent_app_country] => US
[patent_app_date] => 2021-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13417
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17328522
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/328522 | Apparatuses and methods for in-memory operations | May 23, 2021 | Issued |
Array
(
[id] => 18623575
[patent_doc_number] => 11756628
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-12
[patent_title] => Semiconductor memory device with first and second sense amplifiers
[patent_app_type] => utility
[patent_app_number] => 17/326954
[patent_app_country] => US
[patent_app_date] => 2021-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 36
[patent_no_of_words] => 32409
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 330
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326954
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/326954 | Semiconductor memory device with first and second sense amplifiers | May 20, 2021 | Issued |
Array
(
[id] => 17745438
[patent_doc_number] => 11393517
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-19
[patent_title] => Apparatus and methods for writing random access memories
[patent_app_type] => utility
[patent_app_number] => 17/319991
[patent_app_country] => US
[patent_app_date] => 2021-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 17798
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319991
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/319991 | Apparatus and methods for writing random access memories | May 12, 2021 | Issued |