Edgardo Ortiz

Array ( [id] => 4189403 [patent_doc_number] => 06150697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Semiconductor apparatus having high withstand voltage' [patent_app_type] => 1 [patent_app_number] => 9/301562 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 8755 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150697.pdf [firstpage_image] =>[orig_patent_app_number] => 301562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4161794 [patent_doc_number] => 06104085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Semiconductor device and method of producing the same' [patent_app_type] => 1 [patent_app_number] => 9/299663 [patent_app_country] => US [patent_app_date] => 1999-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 7304 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104085.pdf [firstpage_image] =>[orig_patent_app_number] => 299663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4148292 [patent_doc_number] => 06031293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Package-free bonding pad structure' [patent_app_type] => 1 [patent_app_number] => 9/299330 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3212 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031293.pdf [firstpage_image] =>[orig_patent_app_number] => 299330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4111467 [patent_doc_number] => 06023092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Semiconductor resistor for withstanding high voltages' [patent_app_type] => 1 [patent_app_number] => 9/293970 [patent_app_country] => US [patent_app_date] => 1999-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1829 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023092.pdf [firstpage_image] =>[orig_patent_app_number] => 293970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4355019 [patent_doc_number] => 06215138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Semiconductor device and its fabrication method' [patent_app_type] => 1 [patent_app_number] => 9/292631 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 41 [patent_no_of_words] => 10458 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215138.pdf [firstpage_image] =>[orig_patent_app_number] => 292631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4196383 [patent_doc_number] => 06130461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/291042 [patent_app_country] => US [patent_app_date] => 1999-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 88 [patent_figures_cnt] => 154 [patent_no_of_words] => 30114 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130461.pdf [firstpage_image] =>[orig_patent_app_number] => 291042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4223136 [patent_doc_number] => 06087722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Multi-chip package' [patent_app_type] => 1 [patent_app_number] => 9/291913 [patent_app_country] => US [patent_app_date] => 1999-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2100 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087722.pdf [firstpage_image] =>[orig_patent_app_number] => 291913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1221832 [patent_doc_number] => 06703709 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Structures formed using silicide cap as an etch stop in multilayer metal processes' [patent_app_type] => B1 [patent_app_number] => 09/290531 [patent_app_country] => US [patent_app_date] => 1999-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2623 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703709.pdf [firstpage_image] =>[orig_patent_app_number] => 09290531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309848 [patent_doc_number] => 06326657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Semiconductor device having both memory and logic circuit and its manufacture' [patent_app_type] => 1 [patent_app_number] => 9/288302 [patent_app_country] => US [patent_app_date] => 1999-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 9754 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326657.pdf [firstpage_image] =>[orig_patent_app_number] => 288302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1391335 [patent_doc_number] => 06552402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Composite MOS transistor device' [patent_app_type] => B1 [patent_app_number] => 09/287310 [patent_app_country] => US [patent_app_date] => 1999-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4901 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552402.pdf [firstpage_image] =>[orig_patent_app_number] => 09287310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1391335 [patent_doc_number] => 06552402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Composite MOS transistor device' [patent_app_type] => B1 [patent_app_number] => 09/287310 [patent_app_country] => US [patent_app_date] => 1999-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4901 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552402.pdf [firstpage_image] =>[orig_patent_app_number] => 09287310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1391335 [patent_doc_number] => 06552402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Composite MOS transistor device' [patent_app_type] => B1 [patent_app_number] => 09/287310 [patent_app_country] => US [patent_app_date] => 1999-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4901 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552402.pdf [firstpage_image] =>[orig_patent_app_number] => 09287310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1391335 [patent_doc_number] => 06552402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Composite MOS transistor device' [patent_app_type] => B1 [patent_app_number] => 09/287310 [patent_app_country] => US [patent_app_date] => 1999-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4901 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552402.pdf [firstpage_image] =>[orig_patent_app_number] => 09287310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1476300 [patent_doc_number] => 06388288 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Integrating dual supply voltages using a single extra mask level' [patent_app_type] => B1 [patent_app_number] => 09/276783 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2765 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388288.pdf [firstpage_image] =>[orig_patent_app_number] => 09276783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4350922 [patent_doc_number] => 06285059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Structure for laterally diffused metal-oxide semiconductor' [patent_app_type] => 1 [patent_app_number] => 9/271561 [patent_app_country] => US [patent_app_date] => 1999-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1537 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285059.pdf [firstpage_image] =>[orig_patent_app_number] => 271561 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4137329 [patent_doc_number] => 06034425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Flat multiple-chip module micro ball grid array packaging' [patent_app_type] => 1 [patent_app_number] => 9/270802 [patent_app_country] => US [patent_app_date] => 1999-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 1283 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034425.pdf [firstpage_image] =>[orig_patent_app_number] => 270802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4212689 [patent_doc_number] => 06028363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Vertical via/contact' [patent_app_type] => 1 [patent_app_number] => 9/268541 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1560 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028363.pdf [firstpage_image] =>[orig_patent_app_number] => 268541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4239476 [patent_doc_number] => 06075293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Semiconductor device having a multi-layer metal interconnect structure' [patent_app_type] => 1 [patent_app_number] => 9/263412 [patent_app_country] => US [patent_app_date] => 1999-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075293.pdf [firstpage_image] =>[orig_patent_app_number] => 263412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7626559 [patent_doc_number] => 06768203 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-27 [patent_title] => 'Open-bottomed via liner structure and method for fabricating same' [patent_app_type] => B1 [patent_app_number] => 09/262690 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3033 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/768/06768203.pdf [firstpage_image] =>[orig_patent_app_number] => 09262690 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1463662 [patent_doc_number] => 06351009 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'MOS-gated device having a buried gate and process for forming same' [patent_app_type] => B1 [patent_app_number] => 09/260411 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2442 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351009.pdf [firstpage_image] =>[orig_patent_app_number] => 09260411 [rel_patent_id] =>[rel_patent_doc_number] =>)