
Edgardo Ortiz
Examiner (ID: 7554)
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815 |
| Total Applications | 306 |
| Issued Applications | 269 |
| Pending Applications | 3 |
| Abandoned Applications | 34 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18236204
[patent_doc_number] => 11600772
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-07
[patent_title] => Resistance variable device with chalcogen-containing layer
[patent_app_type] => utility
[patent_app_number] => 17/014587
[patent_app_country] => US
[patent_app_date] => 2020-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 4564
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17014587
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/014587 | Resistance variable device with chalcogen-containing layer | Sep 7, 2020 | Issued |
Array
(
[id] => 16716037
[patent_doc_number] => 20210083184
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => SEMICONDUCTOR STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/010382
[patent_app_country] => US
[patent_app_date] => 2020-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15252
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010382
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/010382 | Semiconductor storage device with insulating films adjacent resistance changing films | Sep 1, 2020 | Issued |
Array
(
[id] => 16528490
[patent_doc_number] => 20200402571
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-24
[patent_title] => MEMORY MACRO AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/010483
[patent_app_country] => US
[patent_app_date] => 2020-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10460
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010483
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/010483 | Memory macro and method of operating the same | Sep 1, 2020 | Issued |
Array
(
[id] => 17025563
[patent_doc_number] => 20210249435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-12
[patent_title] => MEMORY DEVICE AND MANUFACTURING METHOD FOR THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/004048
[patent_app_country] => US
[patent_app_date] => 2020-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5658
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004048
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/004048 | Memory device with first switch and word line switches comprising a common control electrode and manufacturing method for the same | Aug 26, 2020 | Issued |
Array
(
[id] => 17040777
[patent_doc_number] => 20210257413
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-19
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/003759
[patent_app_country] => US
[patent_app_date] => 2020-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6806
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003759
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/003759 | Semiconductor memory device with resistance change memory element and manufacturing method of semiconductor memory device with resistance change memory element | Aug 25, 2020 | Issued |
Array
(
[id] => 16920587
[patent_doc_number] => 20210193679
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/993570
[patent_app_country] => US
[patent_app_date] => 2020-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8786
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16993570
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/993570 | Semiconductor memory device with a plurality of amplification stages | Aug 13, 2020 | Issued |
Array
(
[id] => 17469975
[patent_doc_number] => 11276457
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-15
[patent_title] => Processing in memory
[patent_app_type] => utility
[patent_app_number] => 16/989620
[patent_app_country] => US
[patent_app_date] => 2020-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 14721
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16989620
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/989620 | Processing in memory | Aug 9, 2020 | Issued |
Array
(
[id] => 16624987
[patent_doc_number] => 20210043640
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-11
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/986853
[patent_app_country] => US
[patent_app_date] => 2020-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16224
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16986853
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/986853 | Semiconductor memory device with protruding separating portions | Aug 5, 2020 | Issued |
Array
(
[id] => 17380908
[patent_doc_number] => 11238930
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-01
[patent_title] => Method of RRAM WRITE ramping voltage in intervals
[patent_app_type] => utility
[patent_app_number] => 16/984043
[patent_app_country] => US
[patent_app_date] => 2020-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 5661
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16984043
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/984043 | Method of RRAM WRITE ramping voltage in intervals | Aug 2, 2020 | Issued |
Array
(
[id] => 16631860
[patent_doc_number] => 20210050514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-18
[patent_title] => RESISTIVE SWITCHING MEMORY DEVICE BASED ON MULTI-INPUTS
[patent_app_type] => utility
[patent_app_number] => 16/932029
[patent_app_country] => US
[patent_app_date] => 2020-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7986
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932029
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/932029 | Resistive switching memory device based on multi-inputs | Jul 16, 2020 | Issued |
Array
(
[id] => 16904945
[patent_doc_number] => 20210183861
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-17
[patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/930398
[patent_app_country] => US
[patent_app_date] => 2020-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8374
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16930398
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/930398 | Three-dimensional semiconductor device with a bit line perpendicular to a substrate | Jul 15, 2020 | Issued |
Array
(
[id] => 18522012
[patent_doc_number] => 11711922
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-25
[patent_title] => Memory device with memory cells comprising multiple transistors
[patent_app_type] => utility
[patent_app_number] => 16/925648
[patent_app_country] => US
[patent_app_date] => 2020-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 86
[patent_no_of_words] => 39337
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 290
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925648
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/925648 | Memory device with memory cells comprising multiple transistors | Jul 9, 2020 | Issued |
Array
(
[id] => 16781393
[patent_doc_number] => 20210118472
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/918123
[patent_app_country] => US
[patent_app_date] => 2020-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10576
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16918123
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/918123 | Semiconductor device having upper and lower wiring with different grain sizes | Jun 30, 2020 | Issued |
Array
(
[id] => 16455778
[patent_doc_number] => 20200365204
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-19
[patent_title] => SET/RESET METHODS FOR CRYSTALLIZATION IMPROVEMENT IN PHASE CHANGE MEMORIES
[patent_app_type] => utility
[patent_app_number] => 16/912719
[patent_app_country] => US
[patent_app_date] => 2020-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14638
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912719
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/912719 | Set/reset methods for crystallization improvement in phase change memories | Jun 25, 2020 | Issued |
Array
(
[id] => 16528954
[patent_doc_number] => 20200403035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-24
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/908880
[patent_app_country] => US
[patent_app_date] => 2020-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18127
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16908880
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/908880 | MEMORY DEVICE | Jun 22, 2020 | Abandoned |
Array
(
[id] => 16936688
[patent_doc_number] => 20210202577
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-01
[patent_title] => THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICE HAVING RESISTANCE CHANGE STRUCTURE AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/908635
[patent_app_country] => US
[patent_app_date] => 2020-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10358
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16908635
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/908635 | Three-dimensional nonvolatile memory device having resistance change structure and method of operating the same | Jun 21, 2020 | Issued |
Array
(
[id] => 17668434
[patent_doc_number] => 11362139
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-14
[patent_title] => Electronic device and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/903908
[patent_app_country] => US
[patent_app_date] => 2020-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 23
[patent_no_of_words] => 12232
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903908
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/903908 | Electronic device and method of manufacturing the same | Jun 16, 2020 | Issued |
Array
(
[id] => 17652961
[patent_doc_number] => 11355703
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-07
[patent_title] => Phase change device with interfacing first and second semiconductor layers
[patent_app_type] => utility
[patent_app_number] => 16/903245
[patent_app_country] => US
[patent_app_date] => 2020-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 6361
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903245
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/903245 | Phase change device with interfacing first and second semiconductor layers | Jun 15, 2020 | Issued |
Array
(
[id] => 17455913
[patent_doc_number] => 11270779
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-08
[patent_title] => Multi-gate NOR flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates
[patent_app_type] => utility
[patent_app_number] => 16/901758
[patent_app_country] => US
[patent_app_date] => 2020-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 20
[patent_no_of_words] => 12068
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901758
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/901758 | Multi-gate NOR flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates | Jun 14, 2020 | Issued |
Array
(
[id] => 16873818
[patent_doc_number] => 20210167285
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-03
[patent_title] => VARIABLE RESISTANCE MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/898686
[patent_app_country] => US
[patent_app_date] => 2020-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7476
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16898686
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/898686 | Variable resistance memory devices implementing two-dimensional transition metal dichalcogenide materials | Jun 10, 2020 | Issued |