
Edgardo Ortiz
Examiner (ID: 7554)
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815 |
| Total Applications | 306 |
| Issued Applications | 269 |
| Pending Applications | 3 |
| Abandoned Applications | 34 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19648472
[patent_doc_number] => 20240422992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => MEMORY CIRCUIT COMPRISING ELECTRONIC CELLS AND A CONTROL CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/738675
[patent_app_country] => US
[patent_app_date] => 2024-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5193
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738675
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/738675 | MEMORY CIRCUIT COMPRISING ELECTRONIC CELLS AND A CONTROL CIRCUIT | Jun 9, 2024 | Pending |
Array
(
[id] => 19467680
[patent_doc_number] => 20240321350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => REFRESH OF NEIGHBORING MEMORY CELLS BASED ON READ STATUS
[patent_app_type] => utility
[patent_app_number] => 18/734724
[patent_app_country] => US
[patent_app_date] => 2024-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9606
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734724
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/734724 | REFRESH OF NEIGHBORING MEMORY CELLS BASED ON READ STATUS | Jun 4, 2024 | Pending |
Array
(
[id] => 20396710
[patent_doc_number] => 20250372185
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-04
[patent_title] => FAKE FAST PLANE DETECTION IN EARLY PROGRAM TERMINATION
[patent_app_type] => utility
[patent_app_number] => 18/680066
[patent_app_country] => US
[patent_app_date] => 2024-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13251
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680066
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/680066 | Fake fast plane detection in early program termination | May 30, 2024 | Issued |
Array
(
[id] => 20396691
[patent_doc_number] => 20250372166
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-04
[patent_title] => ERASE ALGORITHM FOR NON-VOLATILE MEMORY DEFINING A WEAK PROGRAM STATE AS AN ERASE STATE
[patent_app_type] => utility
[patent_app_number] => 18/678273
[patent_app_country] => US
[patent_app_date] => 2024-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8468
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678273
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/678273 | ERASE ALGORITHM FOR NON-VOLATILE MEMORY DEFINING A WEAK PROGRAM STATE AS AN ERASE STATE | May 29, 2024 | Pending |
Array
(
[id] => 19604420
[patent_doc_number] => 20240395300
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-28
[patent_title] => MRAM BASED ON THE FERROMAGNETIC FILM WITH IN-PLANE BIAXIAL ANISOTROPY
[patent_app_type] => utility
[patent_app_number] => 18/670843
[patent_app_country] => US
[patent_app_date] => 2024-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3659
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 31
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670843
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/670843 | MRAM BASED ON THE FERROMAGNETIC FILM WITH IN-PLANE BIAXIAL ANISOTROPY | May 21, 2024 | Pending |
Array
(
[id] => 20773286
[patent_doc_number] => 12656959
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-16
[patent_title] => Cross temperature NAND read
[patent_app_type] => utility
[patent_app_number] => 18/670485
[patent_app_country] => US
[patent_app_date] => 2024-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 30
[patent_no_of_words] => 15619
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670485
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/670485 | Cross temperature NAND read | May 20, 2024 | Issued |
Array
(
[id] => 20132091
[patent_doc_number] => 12374408
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-29
[patent_title] => Multi-state programming of memory cells
[patent_app_type] => utility
[patent_app_number] => 18/669140
[patent_app_country] => US
[patent_app_date] => 2024-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 5754
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669140
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/669140 | Multi-state programming of memory cells | May 19, 2024 | Issued |
Array
(
[id] => 20675235
[patent_doc_number] => 12615768
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-28
[patent_title] => One-time-programmable memory device
[patent_app_type] => utility
[patent_app_number] => 18/665740
[patent_app_country] => US
[patent_app_date] => 2024-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7984
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665740
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/665740 | One-time-programmable memory device | May 15, 2024 | Issued |
Array
(
[id] => 19559649
[patent_doc_number] => 20240371441
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => CONFIGURATION BIT CIRCUIT FOR PROGRAMMABLE LOGIC DEVICE WITH PHASE CHANGE RANDOM ACCESS MEMORY AND PROGRAM AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/652970
[patent_app_country] => US
[patent_app_date] => 2024-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6352
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652970
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/652970 | CONFIGURATION BIT CIRCUIT FOR PROGRAMMABLE LOGIC DEVICE WITH PHASE CHANGE RANDOM ACCESS MEMORY AND PROGRAM AND OPERATION METHOD THEREOF | May 1, 2024 | Pending |
Array
(
[id] => 19409253
[patent_doc_number] => 20240292764
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-29
[patent_title] => Multi-Bit Storage Device Using Phase Change Material
[patent_app_type] => utility
[patent_app_number] => 18/653418
[patent_app_country] => US
[patent_app_date] => 2024-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8965
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653418
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/653418 | Multi-bit storage device using phase change material | May 1, 2024 | Issued |
Array
(
[id] => 20285998
[patent_doc_number] => 20250311240
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-02
[patent_title] => SCALED ONE TRANSISTOR TWO RESISTOR (1T 2R) MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/621095
[patent_app_country] => US
[patent_app_date] => 2024-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4534
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621095
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/621095 | SCALED ONE TRANSISTOR TWO RESISTOR (1T 2R) MEMORY | Mar 28, 2024 | Pending |
Array
(
[id] => 19467682
[patent_doc_number] => 20240321352
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/603281
[patent_app_country] => US
[patent_app_date] => 2024-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 54612
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603281
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/603281 | Memory device storing a first, second, and third bit | Mar 12, 2024 | Issued |
Array
(
[id] => 19515420
[patent_doc_number] => 20240347106
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-17
[patent_title] => SEMICONDUCTOR DEVICE AND CALCULATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/444730
[patent_app_country] => US
[patent_app_date] => 2024-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6883
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444730
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/444730 | SEMICONDUCTOR DEVICE AND CALCULATING METHOD THEREOF | Feb 17, 2024 | Pending |
Array
(
[id] => 19995748
[patent_doc_number] => 20250133970
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-24
[patent_title] => CHALCOGENIDE-BASED MEMORY DEVICE FOR IMPLEMENTING MULTI-LEVEL MEMORY AND ELECTRONIC APPARATUS INCLUDING THE CHALCOGENIDE-BASED MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/444206
[patent_app_country] => US
[patent_app_date] => 2024-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3188
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444206
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/444206 | CHALCOGENIDE-BASED MEMORY DEVICE FOR IMPLEMENTING MULTI-LEVEL MEMORY AND ELECTRONIC APPARATUS INCLUDING THE CHALCOGENIDE-BASED MEMORY DEVICE | Feb 15, 2024 | Pending |
Array
(
[id] => 19221213
[patent_doc_number] => 20240185917
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => Memory Cells, Memory Cell Arrays, Methods of Using and Methods of Making
[patent_app_type] => utility
[patent_app_number] => 18/441881
[patent_app_country] => US
[patent_app_date] => 2024-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25659
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441881
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/441881 | Memory cell using data storing bipolar device | Feb 13, 2024 | Issued |
Array
(
[id] => 20070552
[patent_doc_number] => 20250208774
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-26
[patent_title] => PROGRAMMABLE LOGIC BLOCK COMPRISING FLASH MEMORY ARRAY TO STORE CONFIGURATION DATA FOR PROGRAMMABLE LOGIC
[patent_app_type] => utility
[patent_app_number] => 18/435943
[patent_app_country] => US
[patent_app_date] => 2024-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3200
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435943
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/435943 | PROGRAMMABLE LOGIC BLOCK COMPRISING FLASH MEMORY ARRAY TO STORE CONFIGURATION DATA FOR PROGRAMMABLE LOGIC | Feb 6, 2024 | Pending |
Array
(
[id] => 19323291
[patent_doc_number] => 20240244839
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/435113
[patent_app_country] => US
[patent_app_date] => 2024-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17666
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 608
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435113
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/435113 | Memory system with a plurality of select string lines | Feb 6, 2024 | Issued |
Array
(
[id] => 19191134
[patent_doc_number] => 20240170047
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => PROCESSING IN MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/430136
[patent_app_country] => US
[patent_app_date] => 2024-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14772
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430136
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/430136 | Processing in memory | Jan 31, 2024 | Issued |
Array
(
[id] => 19175863
[patent_doc_number] => 20240161837
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => MEMORY CIRCUIT, SYSTEM AND METHOD FOR RAPID RETRIEVAL OF DATA SETS
[patent_app_type] => utility
[patent_app_number] => 18/420073
[patent_app_country] => US
[patent_app_date] => 2024-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 34409
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420073
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/420073 | Memory circuit, system and method for rapid retrieval of data sets | Jan 22, 2024 | Issued |
Array
(
[id] => 20113413
[patent_doc_number] => 12364170
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Resistive memory devices using a carbon-based conductor line and methods for forming the same
[patent_app_type] => utility
[patent_app_number] => 18/413107
[patent_app_country] => US
[patent_app_date] => 2024-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 53
[patent_no_of_words] => 6794
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413107
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/413107 | Resistive memory devices using a carbon-based conductor line and methods for forming the same | Jan 15, 2024 | Issued |