Edgardo Ortiz

Array ( [id] => 6753452 [patent_doc_number] => 20030001228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Antistatic contact for a polycrystalline silicon line' [patent_app_type] => new [patent_app_number] => 10/165051 [patent_app_country] => US [patent_app_date] => 2002-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4458 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20030001228.pdf [firstpage_image] =>[orig_patent_app_number] => 10165051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6269482 [patent_doc_number] => 20020105028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/116002 [patent_app_country] => US [patent_app_date] => 2002-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13366 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20020105028.pdf [firstpage_image] =>[orig_patent_app_number] => 10116002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6729942 [patent_doc_number] => 20030186132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Box-in-box field-to-field alignment structure' [patent_app_type] => new [patent_app_number] => 10/114701 [patent_app_country] => US [patent_app_date] => 2002-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2985 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20030186132.pdf [firstpage_image] =>[orig_patent_app_number] => 10114701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1217935 [patent_doc_number] => 06707082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Ferroelectric transistor' [patent_app_type] => B2 [patent_app_number] => 10/112272 [patent_app_country] => US [patent_app_date] => 2002-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2432 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707082.pdf [firstpage_image] =>[orig_patent_app_number] => 10112272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6170125 [patent_doc_number] => 20020153550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'FRAM and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/109432 [patent_app_country] => US [patent_app_date] => 2002-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3436 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20020153550.pdf [firstpage_image] =>[orig_patent_app_number] => 10109432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1144666 [patent_doc_number] => 06777756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/102631 [patent_app_country] => US [patent_app_date] => 2002-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3157 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777756.pdf [firstpage_image] =>[orig_patent_app_number] => 10102631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6827615 [patent_doc_number] => 20030178673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Structures of and methods of fabricating trench-gated MIS devices' [patent_app_type] => new [patent_app_number] => 10/104811 [patent_app_country] => US [patent_app_date] => 2002-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10988 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20030178673.pdf [firstpage_image] =>[orig_patent_app_number] => 10104811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1223823 [patent_doc_number] => 06699795 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'Gate etch process' [patent_app_type] => B1 [patent_app_number] => 10/099841 [patent_app_country] => US [patent_app_date] => 2002-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/699/06699795.pdf [firstpage_image] =>[orig_patent_app_number] => 10099841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7278852 [patent_doc_number] => 20040061229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics' [patent_app_type] => new [patent_app_number] => 10/091795 [patent_app_country] => US [patent_app_date] => 2002-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9210 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20040061229.pdf [firstpage_image] =>[orig_patent_app_number] => 10091795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6832748 [patent_doc_number] => 20030160293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Method of connecting core I/O pins to backside chip I/O pads' [patent_app_type] => new [patent_app_number] => 09/683872 [patent_app_country] => US [patent_app_date] => 2002-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3827 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20030160293.pdf [firstpage_image] =>[orig_patent_app_number] => 09683872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1257283 [patent_doc_number] => 06667528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-23 [patent_title] => 'Semiconductor-on-insulator lateral p-i-n photodetector with a reflecting mirror and backside contact and method for forming the same' [patent_app_type] => B2 [patent_app_number] => 10/033902 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 7947 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/667/06667528.pdf [firstpage_image] =>[orig_patent_app_number] => 10033902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6348868 [patent_doc_number] => 20020056867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Fork-like memory structure for ULSI DRAM and method of fabrication' [patent_app_type] => new [patent_app_number] => 10/038635 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2831 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056867.pdf [firstpage_image] =>[orig_patent_app_number] => 10038635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5918031 [patent_doc_number] => 20020113282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Semiconductor photodetection device' [patent_app_type] => new [patent_app_number] => 10/015681 [patent_app_country] => US [patent_app_date] => 2001-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8361 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20020113282.pdf [firstpage_image] =>[orig_patent_app_number] => 10015681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1399656 [patent_doc_number] => 06545323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Semiconductor memory device including a pair of MOS transistors forming a detection circuit' [patent_app_type] => B2 [patent_app_number] => 10/014662 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 88 [patent_figures_cnt] => 154 [patent_no_of_words] => 30787 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545323.pdf [firstpage_image] =>[orig_patent_app_number] => 10014662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6205331 [patent_doc_number] => 20020070406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Nonvolatile memory and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 09/988729 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12869 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20020070406.pdf [firstpage_image] =>[orig_patent_app_number] => 09988729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1518820 [patent_doc_number] => 06501115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Semiconductor integrated circuit device and process for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/988586 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 7315 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501115.pdf [firstpage_image] =>[orig_patent_app_number] => 09988586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1410224 [patent_doc_number] => 06534830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-18 [patent_title] => 'Low impedance VDMOS semiconductor component' [patent_app_type] => B2 [patent_app_number] => 10/011131 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2209 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534830.pdf [firstpage_image] =>[orig_patent_app_number] => 10011131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6385165 [patent_doc_number] => 20020179978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/986881 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20020179978.pdf [firstpage_image] =>[orig_patent_app_number] => 09986881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6348960 [patent_doc_number] => 20020056883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Radio frequency (RF) power devices having faraday shield layers therein' [patent_app_type] => new [patent_app_number] => 09/993412 [patent_app_country] => US [patent_app_date] => 2001-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 12110 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056883.pdf [firstpage_image] =>[orig_patent_app_number] => 09993412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1246635 [patent_doc_number] => 06677634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/984182 [patent_app_country] => US [patent_app_date] => 2001-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3270 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677634.pdf [firstpage_image] =>[orig_patent_app_number] => 09984182 [rel_patent_id] =>[rel_patent_doc_number] =>)