
Edgardo Ortiz
Examiner (ID: 14813)
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815 |
| Total Applications | 306 |
| Issued Applications | 269 |
| Pending Applications | 3 |
| Abandoned Applications | 34 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1189919
[patent_doc_number] => 06734515
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-05-11
[patent_title] => 'Semiconductor light receiving element'
[patent_app_type] => B1
[patent_app_number] => 09/787502
[patent_app_country] => US
[patent_app_date] => 2001-03-16
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[pdf_file] => patents/06/734/06734515.pdf
[firstpage_image] =>[orig_patent_app_number] => 09787502
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/787502 | Semiconductor light receiving element | Mar 15, 2001 | Issued |
Array
(
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[patent_doc_number] => 20020115290
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[patent_kind] => A1
[patent_issue_date] => 2002-08-22
[patent_title] => 'Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same'
[patent_app_type] => new
[patent_app_number] => 09/792311
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/792311 | Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same | Feb 21, 2001 | Issued |
Array
(
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[patent_doc_number] => 06686668
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[patent_issue_date] => 2004-02-03
[patent_title] => 'Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask'
[patent_app_type] => B2
[patent_app_number] => 09/764833
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/764833 | Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask | Jan 16, 2001 | Issued |
Array
(
[id] => 6300526
[patent_doc_number] => 20020093067
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[patent_issue_date] => 2002-07-18
[patent_title] => 'SUSPENDED MICROMACHINED STRUCTURE'
[patent_app_type] => new
[patent_app_number] => 09/761291
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[patent_app_date] => 2001-01-16
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Array
(
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[patent_issue_date] => 2004-09-21
[patent_title] => 'Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/751551 | Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials | Dec 27, 2000 | Issued |
Array
(
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[patent_title] => 'Compact sensing apparatus having reduced cross section and methods of mounting same'
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Array
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[patent_title] => 'Semiconductor device equipped with semiconductor circuits composed of semiconductor elements and process for production thereof'
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[patent_app_number] => 09/641768
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/641768 | Semiconductor device equipped with semiconductor circuits composed of semiconductor elements and process for production thereof | Aug 20, 2000 | Issued |
Array
(
[id] => 1561718
[patent_doc_number] => 06437393
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[patent_issue_date] => 2002-08-20
[patent_title] => 'Non-volatile memory cell with silicided contacts'
[patent_app_type] => B1
[patent_app_number] => 09/636114
[patent_app_country] => US
[patent_app_date] => 2000-08-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/636114 | Non-volatile memory cell with silicided contacts | Aug 9, 2000 | Issued |
Array
(
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[patent_issue_date] => 2002-09-17
[patent_title] => 'Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride'
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[patent_app_number] => 09/617820
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/617820 | Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride | Jul 16, 2000 | Issued |
Array
(
[id] => 1336362
[patent_doc_number] => 06597011
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[patent_issue_date] => 2003-07-22
[patent_title] => 'Dual non-parallel electronic field electro-optic effect device'
[patent_app_type] => B1
[patent_app_number] => 09/606611
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Array
(
[id] => 1459807
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[patent_title] => 'Dual non-parallel electronic field electro-optic effect device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/612393 | Dual non-parallel electronic field electro-optic effect device | Jun 28, 2000 | Issued |
Array
(
[id] => 7643542
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[patent_issue_date] => 2002-08-06
[patent_title] => 'Method and apparatus for a monolithic integrated MESFET and p-i-n optical receiver'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/573748 | Method and apparatus for a monolithic integrated MESFET and p-i-n optical receiver | May 17, 2000 | Issued |
Array
(
[id] => 1181987
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[patent_issue_date] => 2004-05-25
[patent_title] => '-WO3-gate ISFET devices and method of making the same'
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Array
(
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[patent_title] => 'Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash'
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Array
(
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Array
(
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[patent_title] => 'Semiconductor component and method for producing the same'
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Array
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Array
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Array
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