Search

Edna Wong

Examiner (ID: 7865, Phone: (571)272-1349 , Office: P/1759 )

Most Active Art Unit
1795
Art Unit(s)
1795, 1751, 1753, 1759, 1102, 1741, 1111
Total Applications
2585
Issued Applications
1631
Pending Applications
215
Abandoned Applications
738

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16417055 [patent_doc_number] => 10824953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Reconfigurable array processor for pattern matching [patent_app_type] => utility [patent_app_number] => 14/602059 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14602059 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/602059
Reconfigurable array processor for pattern matching Jan 20, 2015 Issued
Array ( [id] => 11013200 [patent_doc_number] => 20160210153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'ACCELERATED INSTRUCTION EXECUTION' [patent_app_type] => utility [patent_app_number] => 14/599693 [patent_app_country] => US [patent_app_date] => 2015-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14599693 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/599693
Accelerated execution of execute instruction target Jan 18, 2015 Issued
Array ( [id] => 10982590 [patent_doc_number] => 20160179534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'INSTRUCTION LENGTH DECODING' [patent_app_type] => utility [patent_app_number] => 14/580603 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 21671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580603 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/580603
Instruction length decoding Dec 22, 2014 Issued
Array ( [id] => 10982605 [patent_doc_number] => 20160179549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'Instruction and Logic for Loop Stream Detection' [patent_app_type] => utility [patent_app_number] => 14/580498 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 22232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580498 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/580498
Instruction and Logic for Loop Stream Detection Dec 22, 2014 Abandoned
Array ( [id] => 10982600 [patent_doc_number] => 20160179544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'INSTRUCTION AND LOGIC FOR SUPPRESSION OF HARDWARE PREFETCHERS' [patent_app_type] => utility [patent_app_number] => 14/580999 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 21975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580999 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/580999
Instruction and logic for suppression of hardware prefetchers Dec 22, 2014 Issued
Array ( [id] => 10982604 [patent_doc_number] => 20160179548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'INSTRUCTION AND LOGIC TO PERFORM AN INVERSE CENTRIFUGE OPERATION' [patent_app_type] => utility [patent_app_number] => 14/580055 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580055 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/580055
INSTRUCTION AND LOGIC TO PERFORM AN INVERSE CENTRIFUGE OPERATION Dec 21, 2014 Abandoned
Array ( [id] => 10982595 [patent_doc_number] => 20160179539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'INSTRUCTION AND LOGIC TO PERFORM A CENTRIFUGE OPERATION' [patent_app_type] => utility [patent_app_number] => 14/580069 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580069 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/580069
Instruction and logic to perform a centrifuge operation Dec 21, 2014 Issued
Array ( [id] => 10724423 [patent_doc_number] => 20160070571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'REGISTER FILES FOR STORING DATA OPERATED ON BY INSTRUCTIONS OF MULTIPLE WIDTHS' [patent_app_type] => utility [patent_app_number] => 14/574644 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9245 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14574644 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/574644
Register files for storing data operated on by instructions of multiple widths Dec 17, 2014 Issued
Array ( [id] => 11095597 [patent_doc_number] => 20160292566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'SIGNAL PROCESSING MODULE, ESPECIALLY FOR A NEURAL NETWORK AND A NEURONAL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/037659 [patent_app_country] => US [patent_app_date] => 2014-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4352 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15037659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/037659
Signal processing module, especially for a neural network and a neuronal circuit Nov 26, 2014 Issued
Array ( [id] => 9919147 [patent_doc_number] => 20150074352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'Multiprocessor Having Segmented Cache Memory' [patent_app_type] => utility [patent_app_number] => 14/540782 [patent_app_country] => US [patent_app_date] => 2014-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11759 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14540782 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/540782
Multiprocessor Having Segmented Cache Memory Nov 12, 2014 Abandoned
Array ( [id] => 15854671 [patent_doc_number] => 10642619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Branch prediction using multi-way pattern history table (PHT) and global path vector (GPV) [patent_app_type] => utility [patent_app_number] => 14/528214 [patent_app_country] => US [patent_app_date] => 2014-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5008 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14528214 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/528214
Branch prediction using multi-way pattern history table (PHT) and global path vector (GPV) Oct 29, 2014 Issued
Array ( [id] => 11397356 [patent_doc_number] => 20170017892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'SAMPLING VARIABLES FROM PROBABILISTIC MODELS' [patent_app_type] => utility [patent_app_number] => 15/154113 [patent_app_country] => US [patent_app_date] => 2014-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14947 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15154113 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/154113
SAMPLING VARIABLES FROM PROBABILISTIC MODELS Oct 14, 2014 Abandoned
Array ( [id] => 11931548 [patent_doc_number] => 09798545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Anticipated prefetching for a parent core in a multi-core chip' [patent_app_type] => utility [patent_app_number] => 14/501624 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4912 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501624 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501624
Anticipated prefetching for a parent core in a multi-core chip Sep 29, 2014 Issued
Array ( [id] => 16417054 [patent_doc_number] => 10824952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Reconfigurable array processor for pattern matching [patent_app_type] => utility [patent_app_number] => 14/492827 [patent_app_country] => US [patent_app_date] => 2014-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14492827 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/492827
Reconfigurable array processor for pattern matching Sep 21, 2014 Issued
Array ( [id] => 10724426 [patent_doc_number] => 20160070574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'REGISTER FILES FOR STORING DATA OPERATED ON BY INSTRUCTIONS OF MULTIPLE WIDTHS' [patent_app_type] => utility [patent_app_number] => 14/480680 [patent_app_country] => US [patent_app_date] => 2014-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9245 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14480680 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/480680
Register files for storing data operated on by instructions of multiple widths Sep 8, 2014 Issued
Array ( [id] => 13281479 [patent_doc_number] => 10152324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Virtualization in a bi-endian-mode processor architecture [patent_app_type] => utility [patent_app_number] => 14/477899 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8631 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477899 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/477899
Virtualization in a bi-endian-mode processor architecture Sep 4, 2014 Issued
Array ( [id] => 15386853 [patent_doc_number] => 10534611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Branch prediction using multi-way pattern history table (PHT) and global path vector (GPV) [patent_app_type] => utility [patent_app_number] => 14/448030 [patent_app_country] => US [patent_app_date] => 2014-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4979 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14448030 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/448030
Branch prediction using multi-way pattern history table (PHT) and global path vector (GPV) Jul 30, 2014 Issued
Array ( [id] => 10914369 [patent_doc_number] => 20140317388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'APPARATUS AND METHOD FOR SUPPORTING MULTI-MODES OF PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/258622 [patent_app_country] => US [patent_app_date] => 2014-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6209 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14258622 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/258622
APPARATUS AND METHOD FOR SUPPORTING MULTI-MODES OF PROCESSOR Apr 21, 2014 Abandoned
Array ( [id] => 10948807 [patent_doc_number] => 20140351828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'APPARATUS AND METHOD FOR CONTROLLING MULTI-CORE SYSTEM ON CHIP' [patent_app_type] => utility [patent_app_number] => 14/258806 [patent_app_country] => US [patent_app_date] => 2014-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14258806 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/258806
APPARATUS AND METHOD FOR CONTROLLING MULTI-CORE SYSTEM ON CHIP Apr 21, 2014 Abandoned
Array ( [id] => 12011535 [patent_doc_number] => 09804853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Apparatus and method for compressing instruction for VLIW processor, and apparatus and method for fetching instruction' [patent_app_type] => utility [patent_app_number] => 14/258640 [patent_app_country] => US [patent_app_date] => 2014-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6234 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14258640 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/258640
Apparatus and method for compressing instruction for VLIW processor, and apparatus and method for fetching instruction Apr 21, 2014 Issued
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