Search

Edna Wong

Examiner (ID: 7865, Phone: (571)272-1349 , Office: P/1759 )

Most Active Art Unit
1795
Art Unit(s)
1795, 1751, 1753, 1759, 1102, 1741, 1111
Total Applications
2585
Issued Applications
1631
Pending Applications
215
Abandoned Applications
738

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11680221 [patent_doc_number] => 09678752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Scheduling apparatus and method of dynamically setting the size of a rotating register' [patent_app_type] => utility [patent_app_number] => 14/258526 [patent_app_country] => US [patent_app_date] => 2014-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4135 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14258526 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/258526
Scheduling apparatus and method of dynamically setting the size of a rotating register Apr 21, 2014 Issued
Array ( [id] => 10914606 [patent_doc_number] => 20140317626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'PROCESSOR FOR BATCH THREAD PROCESSING, BATCH THREAD PROCESSING METHOD USING THE SAME, AND CODE GENERATION APPARATUS FOR BATCH THREAD PROCESSING' [patent_app_type] => utility [patent_app_number] => 14/258336 [patent_app_country] => US [patent_app_date] => 2014-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6789 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14258336 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/258336
PROCESSOR FOR BATCH THREAD PROCESSING, BATCH THREAD PROCESSING METHOD USING THE SAME, AND CODE GENERATION APPARATUS FOR BATCH THREAD PROCESSING Apr 21, 2014 Abandoned
Array ( [id] => 10941530 [patent_doc_number] => 20140344551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'DUAL-MODE INSTRUCTION FETCHING APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/257067 [patent_app_country] => US [patent_app_date] => 2014-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4200 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14257067 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/257067
DUAL-MODE INSTRUCTION FETCHING APPARATUS AND METHOD Apr 20, 2014 Abandoned
Array ( [id] => 12513600 [patent_doc_number] => 10001998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Dynamically enabled branch prediction [patent_app_type] => utility [patent_app_number] => 14/256347 [patent_app_country] => US [patent_app_date] => 2014-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10256 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14256347 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/256347
Dynamically enabled branch prediction Apr 17, 2014 Issued
Array ( [id] => 10416819 [patent_doc_number] => 20150301829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'SYSTEMS AND METHODS FOR MANAGING BRANCH TARGET BUFFERS IN A MULTI-THREADED DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/256020 [patent_app_country] => US [patent_app_date] => 2014-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14256020 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/256020
SYSTEMS AND METHODS FOR MANAGING BRANCH TARGET BUFFERS IN A MULTI-THREADED DATA PROCESSING SYSTEM Apr 17, 2014 Abandoned
Array ( [id] => 10914357 [patent_doc_number] => 20140317376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'Digital Processor Having Instruction Set with Complex Angle Function' [patent_app_type] => utility [patent_app_number] => 14/255491 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2280 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255491 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/255491
Digital processor having instruction set with complex angle function Apr 16, 2014 Issued
Array ( [id] => 15788877 [patent_doc_number] => 10628163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Processor with variable pre-fetch threshold [patent_app_type] => utility [patent_app_number] => 14/255077 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5121 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255077 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/255077
Processor with variable pre-fetch threshold Apr 16, 2014 Issued
Array ( [id] => 11924668 [patent_doc_number] => 09792252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Incorporating a spatial array into one or more programmable processor cores' [patent_app_type] => utility [patent_app_number] => 14/252101 [patent_app_country] => US [patent_app_date] => 2014-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14252101 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/252101
Incorporating a spatial array into one or more programmable processor cores Apr 13, 2014 Issued
Array ( [id] => 10408758 [patent_doc_number] => 20150293767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'ROTATING REGISTER FILE WITH BIT EXPANSION SUPPORT' [patent_app_type] => utility [patent_app_number] => 14/251117 [patent_app_country] => US [patent_app_date] => 2014-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14251117 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/251117
ROTATING REGISTER FILE WITH BIT EXPANSION SUPPORT Apr 10, 2014 Abandoned
Array ( [id] => 10907487 [patent_doc_number] => 20140310501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'APPARATUS AND METHOD FOR CALCULATING PHYSICAL ADDRESS OF A PROCESSOR REGISTER' [patent_app_type] => utility [patent_app_number] => 14/248731 [patent_app_country] => US [patent_app_date] => 2014-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14248731 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/248731
APPARATUS AND METHOD FOR CALCULATING PHYSICAL ADDRESS OF A PROCESSOR REGISTER Apr 8, 2014 Abandoned
Array ( [id] => 13212625 [patent_doc_number] => 10120682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Virtualization in a bi-endian-mode processor architecture [patent_app_type] => utility [patent_app_number] => 14/193610 [patent_app_country] => US [patent_app_date] => 2014-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8500 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14193610 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/193610
Virtualization in a bi-endian-mode processor architecture Feb 27, 2014 Issued
Array ( [id] => 10046491 [patent_doc_number] => 09086888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Using a plurality of tables for improving performance in predicting branches in processor instructions' [patent_app_type] => utility [patent_app_number] => 14/174966 [patent_app_country] => US [patent_app_date] => 2014-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9336 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14174966 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/174966
Using a plurality of tables for improving performance in predicting branches in processor instructions Feb 6, 2014 Issued
Array ( [id] => 9493103 [patent_doc_number] => 20140143509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'METHOD AND DEVICE FOR DATA PROCESSING' [patent_app_type] => utility [patent_app_number] => 14/162704 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11506 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14162704 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/162704
METHOD AND DEVICE FOR DATA PROCESSING Jan 22, 2014 Abandoned
Array ( [id] => 9479654 [patent_doc_number] => 20140137117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'VIRTUALIZATION PLANNING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/158726 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14158726 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/158726
Virtualization planning system Jan 16, 2014 Issued
Array ( [id] => 11614390 [patent_doc_number] => 09652246 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-16 [patent_title] => 'Banked physical register data flow architecture in out-of-order processors' [patent_app_type] => utility [patent_app_number] => 14/137519 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14137519 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/137519
Banked physical register data flow architecture in out-of-order processors Dec 19, 2013 Issued
Array ( [id] => 10293088 [patent_doc_number] => 20150178087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'Predicated Vector Hazard Check Instruction' [patent_app_type] => utility [patent_app_number] => 14/137232 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14137232 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/137232
Predicated vector hazard check instruction Dec 19, 2013 Issued
Array ( [id] => 11070203 [patent_doc_number] => 20160267168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'RESIDUAL DATA IDENTIFICATION' [patent_app_type] => utility [patent_app_number] => 15/033181 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6802 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15033181 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/033181
RESIDUAL DATA IDENTIFICATION Dec 18, 2013 Abandoned
Array ( [id] => 11070429 [patent_doc_number] => 20160267393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'METHOD OF CONSTRUCTION AND SELECTION OF PROBALISTIC GRAPHICAL MODELS' [patent_app_type] => utility [patent_app_number] => 15/033159 [patent_app_country] => US [patent_app_date] => 2013-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2584 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15033159 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/033159
METHOD OF CONSTRUCTION AND SELECTION OF PROBALISTIC GRAPHICAL MODELS Oct 29, 2013 Abandoned
Array ( [id] => 9320548 [patent_doc_number] => 20140052886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'All-to-All Comparisons on Architectures Having Limited Storage Space' [patent_app_type] => utility [patent_app_number] => 14/061389 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8804 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061389 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/061389
All-to-all comparisons on architectures having limited storage space Oct 22, 2013 Issued
Array ( [id] => 10228198 [patent_doc_number] => 20150113191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'RESOURCE SERIALIZATION IN A TRANSACTIONAL EXECUTION FACILITY' [patent_app_type] => utility [patent_app_number] => 14/055936 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14055936 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/055936
RESOURCE SERIALIZATION IN A TRANSACTIONAL EXECUTION FACILITY Oct 16, 2013 Abandoned
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