Search

Edna Wong

Examiner (ID: 7865, Phone: (571)272-1349 , Office: P/1759 )

Most Active Art Unit
1795
Art Unit(s)
1795, 1751, 1753, 1759, 1102, 1741, 1111
Total Applications
2585
Issued Applications
1631
Pending Applications
215
Abandoned Applications
738

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9386459 [patent_doc_number] => 20140089942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'SYSTEM TO PROFILE AND OPTIMIZE USER SOFTWARE IN A MANAGED RUN-TIME ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 14/036768 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14552 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14036768 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/036768
System to profile and optimize user software in a managed run-time environment Sep 24, 2013 Issued
Array ( [id] => 9213899 [patent_doc_number] => 20140013076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'EFFICIENT HARDWARE INSTRUCTIONS FOR SINGLE INSTRUCTION MULTIPLE DATA PROCESSORS' [patent_app_type] => utility [patent_app_number] => 14/023064 [patent_app_country] => US [patent_app_date] => 2013-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12944 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14023064 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/023064
Loading values from a value vector into subregisters of a single instruction multiple data register Sep 9, 2013 Issued
Array ( [id] => 9213900 [patent_doc_number] => 20140013077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'EFFICIENT HARDWARE INSTRUCTIONS FOR SINGLE INSTRUCTION MULTIPLE DATA PROCESSORS' [patent_app_type] => utility [patent_app_number] => 14/023249 [patent_app_country] => US [patent_app_date] => 2013-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12719 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14023249 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/023249
Efficient hardware instructions for processing bit vectors for single instruction multiple data processors Sep 9, 2013 Issued
Array ( [id] => 11780722 [patent_doc_number] => 09389904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Apparatus, system and method for heterogeneous data sharing' [patent_app_type] => utility [patent_app_number] => 13/955991 [patent_app_country] => US [patent_app_date] => 2013-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13955991 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/955991
Apparatus, system and method for heterogeneous data sharing Jul 30, 2013 Issued
Array ( [id] => 9150495 [patent_doc_number] => 20130305018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'MFENCE and LFENCE Micro-Architectural Implementation Method and System' [patent_app_type] => utility [patent_app_number] => 13/942660 [patent_app_country] => US [patent_app_date] => 2013-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5347 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13942660 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/942660
MFENCE and LFENCE micro-architectural implementation method and system Jul 14, 2013 Issued
Array ( [id] => 10335333 [patent_doc_number] => 20150220338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'SOFTWARE POLLING ELISION WITH RESTRICTED TRANSACTIONAL MEMORY' [patent_app_type] => utility [patent_app_number] => 14/127988 [patent_app_country] => US [patent_app_date] => 2013-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4685 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14127988 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/127988
SOFTWARE POLLING ELISION WITH RESTRICTED TRANSACTIONAL MEMORY Jun 17, 2013 Abandoned
Array ( [id] => 10228258 [patent_doc_number] => 20150113252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'THREAD CONTROL AND CALLING METHOD OF MULTI-THREAD VIRTUAL PIPELINE (MVP) PROCESSOR, AND PROCESSOR THEREOF' [patent_app_type] => utility [patent_app_number] => 14/353110 [patent_app_country] => US [patent_app_date] => 2013-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5323 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14353110 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/353110
THREAD CONTROL AND CALLING METHOD OF MULTI-THREAD VIRTUAL PIPELINE (MVP) PROCESSOR, AND PROCESSOR THEREOF Jun 6, 2013 Abandoned
Array ( [id] => 9017357 [patent_doc_number] => 20130232321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'Unpacking Packed Data In Multiple Lanes' [patent_app_type] => utility [patent_app_number] => 13/837908 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13837908 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/837908
Unpacking packed data in multiple lanes Mar 14, 2013 Issued
Array ( [id] => 10623368 [patent_doc_number] => 09342310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'MFENCE and LFENCE micro-architectural implementation method and system' [patent_app_type] => utility [patent_app_number] => 13/838229 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5259 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13838229 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/838229
MFENCE and LFENCE micro-architectural implementation method and system Mar 14, 2013 Issued
Array ( [id] => 9341442 [patent_doc_number] => 20140068226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'VECTOR INSTRUCTIONS TO ENABLE EFFICIENT SYNCHRONIZATION AND PARALLEL REDUCTION OPERATIONS' [patent_app_type] => utility [patent_app_number] => 13/795234 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7586 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795234 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795234
Vector instructions to enable efficient synchronization and parallel reduction operations Mar 11, 2013 Issued
Array ( [id] => 9308547 [patent_doc_number] => 20140047221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'FUSING FLAG-PRODUCING AND FLAG-CONSUMING INSTRUCTIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA' [patent_app_type] => utility [patent_app_number] => 13/788008 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12197 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788008 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/788008
FUSING FLAG-PRODUCING AND FLAG-CONSUMING INSTRUCTIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA Mar 6, 2013 Abandoned
13/787907 PREVENTING EXECUTION OF PARITY-ERROR-INDUCED UNPREDICTABLE INSTRUCTIONS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA Mar 6, 2013 Abandoned
Array ( [id] => 11465671 [patent_doc_number] => 09582302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'System and method for managing code isolation' [patent_app_type] => utility [patent_app_number] => 13/788259 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 9219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788259 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/788259
System and method for managing code isolation Mar 6, 2013 Issued
Array ( [id] => 9036243 [patent_doc_number] => 20130238881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'DATA TRANSMISSION DEVICE, DATA TRANSMISSION METHOD, AND COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 13/787682 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6054 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/787682
DATA TRANSMISSION DEVICE, DATA TRANSMISSION METHOD, AND COMPUTER PROGRAM PRODUCT Mar 5, 2013 Abandoned
Array ( [id] => 12173773 [patent_doc_number] => 09891917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'System and method to increase lockstep core availability' [patent_app_type] => utility [patent_app_number] => 13/786550 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6206 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786550 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786550
System and method to increase lockstep core availability Mar 5, 2013 Issued
Array ( [id] => 11924536 [patent_doc_number] => 09792120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Anticipated prefetching for a parent core in a multi-core chip' [patent_app_type] => utility [patent_app_number] => 13/785394 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4880 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13785394 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/785394
Anticipated prefetching for a parent core in a multi-core chip Mar 4, 2013 Issued
Array ( [id] => 9722979 [patent_doc_number] => 20140258680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'PARALLEL DISPATCH OF COPROCESSOR INSTRUCTIONS IN A MULTI-THREAD PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/785017 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9111 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13785017 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/785017
PARALLEL DISPATCH OF COPROCESSOR INSTRUCTIONS IN A MULTI-THREAD PROCESSOR Mar 4, 2013 Abandoned
Array ( [id] => 9722995 [patent_doc_number] => 20140258696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'STRIDED TARGET ADDRESS PREDICTOR (STAP) FOR INDIRECT BRANCHES' [patent_app_type] => utility [patent_app_number] => 13/784964 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3659 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13784964 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/784964
STRIDED TARGET ADDRESS PREDICTOR (STAP) FOR INDIRECT BRANCHES Mar 4, 2013 Abandoned
13/783209 RECONFIGURABLE GRAPH PROCESSOR Feb 28, 2013 Abandoned
Array ( [id] => 9688221 [patent_doc_number] => 20140244986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'SYSTEM AND METHOD TO SELECT A PACKET FORMAT BASED ON A NUMBER OF EXECUTED THREADS' [patent_app_type] => utility [patent_app_number] => 13/776947 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12450 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776947 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/776947
System and method to select a packet format based on a number of executed threads Feb 25, 2013 Issued
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