Search

Edna Wong

Examiner (ID: 7865, Phone: (571)272-1349 , Office: P/1759 )

Most Active Art Unit
1795
Art Unit(s)
1795, 1751, 1753, 1759, 1102, 1741, 1111
Total Applications
2585
Issued Applications
1631
Pending Applications
215
Abandoned Applications
738

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9006124 [patent_doc_number] => 20130227249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'Three-Dimensional Permute Unit for a Single-Instruction Multiple-Data Processor' [patent_app_type] => utility [patent_app_number] => 13/775355 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8059 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13775355 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/775355
Three-dimensional permute unit for a single-instruction multiple-data processor Feb 24, 2013 Issued
Array ( [id] => 9688211 [patent_doc_number] => 20140244976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'IT INSTRUCTION PRE-DECODE' [patent_app_type] => utility [patent_app_number] => 13/774093 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774093 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/774093
IT instruction pre-decode Feb 21, 2013 Issued
Array ( [id] => 9688212 [patent_doc_number] => 20140244977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'Deferred Saving of Registers in a Shared Register Pool for a Multithreaded Microprocessor' [patent_app_type] => utility [patent_app_number] => 13/774140 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6178 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774140 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/774140
Deferred Saving of Registers in a Shared Register Pool for a Multithreaded Microprocessor Feb 21, 2013 Abandoned
Array ( [id] => 9688222 [patent_doc_number] => 20140244987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'Precision Exception Signaling for Multiple Data Architecture' [patent_app_type] => utility [patent_app_number] => 13/773818 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13773818 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/773818
Precision Exception Signaling for Multiple Data Architecture Feb 21, 2013 Abandoned
Array ( [id] => 9176339 [patent_doc_number] => 20130318324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'MINICORE-BASED RECONFIGURABLE PROCESSOR AND METHOD OF FLEXIBLY PROCESSING MULTIPLE DATA USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/766173 [patent_app_country] => US [patent_app_date] => 2013-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5033 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13766173 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/766173
MINICORE-BASED RECONFIGURABLE PROCESSOR AND METHOD OF FLEXIBLY PROCESSING MULTIPLE DATA USING THE SAME Feb 12, 2013 Abandoned
Array ( [id] => 13817601 [patent_doc_number] => 10185569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Precise-restartable parallel execution of programs [patent_app_type] => utility [patent_app_number] => 13/766053 [patent_app_country] => US [patent_app_date] => 2013-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7851 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13766053 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/766053
Precise-restartable parallel execution of programs Feb 12, 2013 Issued
Array ( [id] => 11345193 [patent_doc_number] => 09529599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Dynamic propagation with iterative pipeline processing' [patent_app_type] => utility [patent_app_number] => 13/764905 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 12062 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13764905 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/764905
Dynamic propagation with iterative pipeline processing Feb 11, 2013 Issued
Array ( [id] => 9658714 [patent_doc_number] => 20140229720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'BRANCH PREDICTION WITH POWER USAGE PREDICTION AND CONTROL' [patent_app_type] => utility [patent_app_number] => 13/762621 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10113 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762621 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762621
Branch prediction with power usage prediction and control Feb 7, 2013 Issued
Array ( [id] => 12100982 [patent_doc_number] => 09858077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media' [patent_app_type] => utility [patent_app_number] => 13/741849 [patent_app_country] => US [patent_app_date] => 2013-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8387 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13741849 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/741849
Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media Jan 14, 2013 Issued
Array ( [id] => 9571606 [patent_doc_number] => 20140189319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'Opportunistic Utilization of Redundant ALU' [patent_app_type] => utility [patent_app_number] => 13/729135 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4239 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13729135 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/729135
Opportunistic utilization of redundant ALU Dec 27, 2012 Issued
Array ( [id] => 12011521 [patent_doc_number] => 09804839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Instruction for determining histograms' [patent_app_type] => utility [patent_app_number] => 13/730647 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 16503 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730647 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730647
Instruction for determining histograms Dec 27, 2012 Issued
Array ( [id] => 11584723 [patent_doc_number] => 09639365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Indirect function call instructions in a synchronous parallel thread processor' [patent_app_type] => utility [patent_app_number] => 13/674890 [patent_app_country] => US [patent_app_date] => 2012-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 16414 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13674890 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/674890
Indirect function call instructions in a synchronous parallel thread processor Nov 11, 2012 Issued
Array ( [id] => 9688217 [patent_doc_number] => 20140244982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'PERFORMING STENCIL COMPUTATIONS' [patent_app_type] => utility [patent_app_number] => 14/352870 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14352870 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/352870
Performing stencil computations Nov 7, 2012 Issued
Array ( [id] => 10616553 [patent_doc_number] => 09335997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Processing vectors using a wrapping rotate previous instruction in the macroscalar architecture' [patent_app_type] => utility [patent_app_number] => 13/630596 [patent_app_country] => US [patent_app_date] => 2012-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 17656 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13630596 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/630596
Processing vectors using a wrapping rotate previous instruction in the macroscalar architecture Sep 27, 2012 Issued
Array ( [id] => 8619359 [patent_doc_number] => 20130024672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'PROCESSING VECTORS USING WRAPPING PROPAGATE INSTRUCTIONS IN THE MACROSCALAR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/630328 [patent_app_country] => US [patent_app_date] => 2012-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17513 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13630328 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/630328
Processing vectors using wrapping propagate instructions in the macroscalar architecture Sep 27, 2012 Issued
Array ( [id] => 10623365 [patent_doc_number] => 09342304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Processing vectors using wrapping increment and decrement instructions in the macroscalar architecture' [patent_app_type] => utility [patent_app_number] => 13/628826 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 49630 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628826 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628826
Processing vectors using wrapping increment and decrement instructions in the macroscalar architecture Sep 26, 2012 Issued
Array ( [id] => 10058908 [patent_doc_number] => 09098268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'MFENCE and LFENCE micro-architectural implementation method and system' [patent_app_type] => utility [patent_app_number] => 13/619832 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5254 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13619832 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/619832
MFENCE and LFENCE micro-architectural implementation method and system Sep 13, 2012 Issued
Array ( [id] => 8709910 [patent_doc_number] => 20130067200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/619919 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5255 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13619919 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/619919
MFENCE and LFENCE micro-architectural implementation method and system Sep 13, 2012 Issued
Array ( [id] => 9109878 [patent_doc_number] => 20130283010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => '3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS FOR MULTIMODAL OPERATION OF SAME' [patent_app_type] => utility [patent_app_number] => 13/601289 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11985 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13601289 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/601289
3-D stacked multiprocessor structures and methods for multimodal operation of same Aug 30, 2012 Issued
Array ( [id] => 8639751 [patent_doc_number] => 20130031554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'HARDWARE ACCELERATION' [patent_app_type] => utility [patent_app_number] => 13/572921 [patent_app_country] => US [patent_app_date] => 2012-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5291 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13572921 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/572921
Hardware acceleration wait time awareness in central processing units with multi-thread architectures Aug 12, 2012 Issued
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