Search

Edna Wong

Examiner (ID: 7865, Phone: (571)272-1349 , Office: P/1759 )

Most Active Art Unit
1795
Art Unit(s)
1795, 1751, 1753, 1759, 1102, 1741, 1111
Total Applications
2585
Issued Applications
1631
Pending Applications
215
Abandoned Applications
738

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10091872 [patent_doc_number] => 09128697 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-08 [patent_title] => 'Computer numerical storage format with precision type indicator' [patent_app_type] => utility [patent_app_number] => 13/403618 [patent_app_country] => US [patent_app_date] => 2012-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13403618 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/403618
Computer numerical storage format with precision type indicator Feb 22, 2012 Issued
Array ( [id] => 10091706 [patent_doc_number] => 09128531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Operand special case handling for multi-lane processing' [patent_app_type] => utility [patent_app_number] => 13/402280 [patent_app_country] => US [patent_app_date] => 2012-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4597 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13402280 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/402280
Operand special case handling for multi-lane processing Feb 21, 2012 Issued
Array ( [id] => 9604825 [patent_doc_number] => 20140201506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'METHOD FOR DETERMINING INSTRUCTION ORDER USING TRIGGERS' [patent_app_type] => utility [patent_app_number] => 13/997021 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3554 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997021 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997021
METHOD FOR DETERMINING INSTRUCTION ORDER USING TRIGGERS Dec 29, 2011 Abandoned
Array ( [id] => 9618223 [patent_doc_number] => 20140208080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'APPARATUS AND METHOD FOR DOWN CONVERSION OF DATA TYPES' [patent_app_type] => utility [patent_app_number] => 13/997006 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14863 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997006 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997006
Apparatus and method for down conversion of data types Dec 22, 2011 Issued
Array ( [id] => 13029171 [patent_doc_number] => 10037205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Instruction and logic to provide vector blend and permute functionality [patent_app_type] => utility [patent_app_number] => 13/977734 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 15961 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977734 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977734
Instruction and logic to provide vector blend and permute functionality Dec 22, 2011 Issued
Array ( [id] => 11931550 [patent_doc_number] => 09798548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Methods and apparatus for scheduling instructions using pre-decode data' [patent_app_type] => utility [patent_app_number] => 13/333879 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 12391 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333879 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333879
Methods and apparatus for scheduling instructions using pre-decode data Dec 20, 2011 Issued
Array ( [id] => 8568703 [patent_doc_number] => 20120331274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'Instruction Execution' [patent_app_type] => utility [patent_app_number] => 13/333939 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3182 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333939 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333939
Executing an instruction set using a prefix to interpret an operator field as either a first or a second operator field Dec 20, 2011 Issued
Array ( [id] => 13919663 [patent_doc_number] => 10203954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Instruction and logic to provide conversions between a mask register and a general purpose register or memory [patent_app_type] => utility [patent_app_number] => 13/977732 [patent_app_country] => US [patent_app_date] => 2011-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 16203 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977732 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977732
Instruction and logic to provide conversions between a mask register and a general purpose register or memory Nov 24, 2011 Issued
Array ( [id] => 8267344 [patent_doc_number] => 20120166774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'COMPUTER-READABLE MEDIUM STORING PROCESSOR TESTING PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/281074 [patent_app_country] => US [patent_app_date] => 2011-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12393 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13281074 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/281074
COMPUTER-READABLE MEDIUM STORING PROCESSOR TESTING PROGRAM Oct 24, 2011 Abandoned
Array ( [id] => 11889964 [patent_doc_number] => 09760526 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-12 [patent_title] => 'Multiprocessor messaging system' [patent_app_type] => utility [patent_app_number] => 13/251155 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2657 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251155 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251155
Multiprocessor messaging system Sep 29, 2011 Issued
Array ( [id] => 9520193 [patent_doc_number] => 20140156685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'Loopback structure and data loopback processing method of processor' [patent_app_type] => utility [patent_app_number] => 14/117244 [patent_app_country] => US [patent_app_date] => 2011-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14117244 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/117244
Loopback structure and data loopback processing method of processor Sep 14, 2011 Abandoned
Array ( [id] => 7575423 [patent_doc_number] => 20110271079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'MULTIPLE-CORE PROCESSOR SUPPORTING MULTIPLE INSTRUCTION SET ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 13/182181 [patent_app_country] => US [patent_app_date] => 2011-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20110271079.pdf [firstpage_image] =>[orig_patent_app_number] => 13182181 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/182181
Multiple-core processor supporting multiple instruction set architectures Jul 12, 2011 Issued
Array ( [id] => 7780580 [patent_doc_number] => 20120042136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'Alignment control' [patent_app_type] => utility [patent_app_number] => 13/067805 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20120042136.pdf [firstpage_image] =>[orig_patent_app_number] => 13067805 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/067805
Stack pointer and memory access alignment control Jun 27, 2011 Issued
Array ( [id] => 8213892 [patent_doc_number] => 20120131313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'Error recovery following speculative execution with an instruction processing pipeline' [patent_app_type] => utility [patent_app_number] => 13/067510 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5670 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20120131313.pdf [firstpage_image] =>[orig_patent_app_number] => 13067510 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/067510
Error recovery following speculative execution with an instruction processing pipeline Jun 5, 2011 Issued
Array ( [id] => 8511898 [patent_doc_number] => 20120311307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'Method And Apparatus For Obtaining A Call Stack To An Event Of Interest And Analyzing The Same' [patent_app_type] => utility [patent_app_number] => 13/118766 [patent_app_country] => US [patent_app_date] => 2011-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7450 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13118766 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/118766
Method and apparatus for obtaining a call stack to an event of interest and analyzing the same May 30, 2011 Issued
Array ( [id] => 8504527 [patent_doc_number] => 20120303935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'MICROPROCESSOR SYSTEMS AND METHODS FOR HANDLING INSTRUCTIONS WITH MULTIPLE DEPENDENCIES' [patent_app_type] => utility [patent_app_number] => 13/116325 [patent_app_country] => US [patent_app_date] => 2011-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13116325 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/116325
Microprocessor systems and methods for handling instructions with multiple dependencies May 25, 2011 Issued
Array ( [id] => 8504531 [patent_doc_number] => 20120303938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'PERFORMANCE IN PREDICTING BRANCHES' [patent_app_type] => utility [patent_app_number] => 13/116515 [patent_app_country] => US [patent_app_date] => 2011-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9335 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13116515 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/116515
Performance in predicting branches May 25, 2011 Issued
Array ( [id] => 8504526 [patent_doc_number] => 20120303934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'METHOD AND APPARATUS FOR GENERATING AN ENHANCED PROCESSOR RESYNC INDICATOR SIGNAL USING HASH FUNCTIONS AND A LOAD TRACKING UNIT' [patent_app_type] => utility [patent_app_number] => 13/116414 [patent_app_country] => US [patent_app_date] => 2011-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5179 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13116414 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/116414
METHOD AND APPARATUS FOR GENERATING AN ENHANCED PROCESSOR RESYNC INDICATOR SIGNAL USING HASH FUNCTIONS AND A LOAD TRACKING UNIT May 25, 2011 Abandoned
Array ( [id] => 9847647 [patent_doc_number] => 08949581 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-03 [patent_title] => 'Threshold controlled limited out of order load execution' [patent_app_type] => utility [patent_app_number] => 13/103833 [patent_app_country] => US [patent_app_date] => 2011-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7827 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13103833 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/103833
Threshold controlled limited out of order load execution May 8, 2011 Issued
Array ( [id] => 9834467 [patent_doc_number] => 08943301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Storing branch information in an address table of a processor' [patent_app_type] => utility [patent_app_number] => 13/101650 [patent_app_country] => US [patent_app_date] => 2011-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6060 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13101650 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/101650
Storing branch information in an address table of a processor May 4, 2011 Issued
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