Search

Edna Wong

Examiner (ID: 7865, Phone: (571)272-1349 , Office: P/1759 )

Most Active Art Unit
1795
Art Unit(s)
1795, 1751, 1753, 1759, 1102, 1741, 1111
Total Applications
2585
Issued Applications
1631
Pending Applications
215
Abandoned Applications
738

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10058935 [patent_doc_number] => 09098295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Predicting a result for an actual instruction when processing vector instructions' [patent_app_type] => utility [patent_app_number] => 13/090964 [patent_app_country] => US [patent_app_date] => 2011-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 12313 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13090964 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/090964
Predicting a result for an actual instruction when processing vector instructions Apr 19, 2011 Issued
Array ( [id] => 10085137 [patent_doc_number] => 09122485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-01 [patent_title] => 'Predicting a result of a dependency-checking instruction when processing vector instructions' [patent_app_type] => utility [patent_app_number] => 13/090001 [patent_app_country] => US [patent_app_date] => 2011-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 11032 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13090001 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/090001
Predicting a result of a dependency-checking instruction when processing vector instructions Apr 18, 2011 Issued
Array ( [id] => 10589479 [patent_doc_number] => 09311094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Predicting a pattern in addresses for a memory-accessing instruction when processing vector instructions' [patent_app_type] => utility [patent_app_number] => 13/090131 [patent_app_country] => US [patent_app_date] => 2011-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 9619 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13090131 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/090131
Predicting a pattern in addresses for a memory-accessing instruction when processing vector instructions Apr 18, 2011 Issued
Array ( [id] => 10117538 [patent_doc_number] => 09152423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Method and apparatus for efficient loop instruction execution using bit vector scanning' [patent_app_type] => utility [patent_app_number] => 13/071730 [patent_app_country] => US [patent_app_date] => 2011-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4974 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13071730 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/071730
Method and apparatus for efficient loop instruction execution using bit vector scanning Mar 24, 2011 Issued
Array ( [id] => 7493007 [patent_doc_number] => 20110238960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'DISTRIBUTED PROCESSING SYSTEM, CONTROL UNIT, PROCESSING ELEMENT, DISTRIBUTED PROCESSING METHOD AND COMPUTER PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/070644 [patent_app_country] => US [patent_app_date] => 2011-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 18088 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20110238960.pdf [firstpage_image] =>[orig_patent_app_number] => 13070644 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/070644
DISTRIBUTED PROCESSING SYSTEM, CONTROL UNIT, PROCESSING ELEMENT, DISTRIBUTED PROCESSING METHOD AND COMPUTER PROGRAM Mar 23, 2011 Abandoned
Array ( [id] => 7493013 [patent_doc_number] => 20110238966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'BRANCH PREDICTION METHOD AND BRANCH PREDICTION CIRCUIT FOR EXECUTING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/070983 [patent_app_country] => US [patent_app_date] => 2011-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7896 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20110238966.pdf [firstpage_image] =>[orig_patent_app_number] => 13070983 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/070983
BRANCH PREDICTION METHOD AND BRANCH PREDICTION CIRCUIT FOR EXECUTING THE SAME Mar 23, 2011 Abandoned
Array ( [id] => 7493006 [patent_doc_number] => 20110238959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'DISTRIBUTED CONTROLLER, DISTRIBUTED PROCESSING SYSTEM, AND DISTRIBUTED PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 13/069757 [patent_app_country] => US [patent_app_date] => 2011-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 13838 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20110238959.pdf [firstpage_image] =>[orig_patent_app_number] => 13069757 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/069757
DISTRIBUTED CONTROLLER, DISTRIBUTED PROCESSING SYSTEM, AND DISTRIBUTED PROCESSING METHOD Mar 22, 2011 Abandoned
Array ( [id] => 12011532 [patent_doc_number] => 09804851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Operand size control' [patent_app_type] => utility [patent_app_number] => 13/064257 [patent_app_country] => US [patent_app_date] => 2011-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5058 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13064257 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/064257
Operand size control Mar 13, 2011 Issued
Array ( [id] => 11795854 [patent_doc_number] => 09405683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-02 [patent_title] => 'Processor and memory control method for allocating instructions to a cache and a scratch pad memory' [patent_app_type] => utility [patent_app_number] => 13/045752 [patent_app_country] => US [patent_app_date] => 2011-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6959 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13045752 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/045752
Processor and memory control method for allocating instructions to a cache and a scratch pad memory Mar 10, 2011 Issued
Array ( [id] => 6104939 [patent_doc_number] => 20110167241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'SUPERCONDUCTING CIRCUIT FOR HIGH-SPEED LOOKUP TABLE' [patent_app_type] => utility [patent_app_number] => 13/043272 [patent_app_country] => US [patent_app_date] => 2011-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3808 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20110167241.pdf [firstpage_image] =>[orig_patent_app_number] => 13043272 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/043272
SUPERCONDUCTING CIRCUIT FOR HIGH-SPEED LOOKUP TABLE Mar 7, 2011 Abandoned
Array ( [id] => 8372444 [patent_doc_number] => 20120221832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'APPARATUS AND METHODS FOR IN-APPLICATION PROGRAMMING OF FLASH-BASED PROGRAMABLE LOGIC DEVICES' [patent_app_type] => utility [patent_app_number] => 13/037058 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2187 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13037058 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/037058
Apparatus and methods for in-application programming of flash-based programable logic devices Feb 27, 2011 Issued
Array ( [id] => 6020312 [patent_doc_number] => 20110225395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'DATA PROCESSING SYSTEM AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/033072 [patent_app_country] => US [patent_app_date] => 2011-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7029 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225395.pdf [firstpage_image] =>[orig_patent_app_number] => 13033072 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/033072
DATA PROCESSING SYSTEM AND CONTROL METHOD THEREOF Feb 22, 2011 Abandoned
Array ( [id] => 6020316 [patent_doc_number] => 20110225397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'Mapping between registers used by multiple instruction sets' [patent_app_type] => utility [patent_app_number] => 12/929865 [patent_app_country] => US [patent_app_date] => 2011-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6554 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225397.pdf [firstpage_image] =>[orig_patent_app_number] => 12929865 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/929865
Mapping between registers used by multiple instruction sets Feb 21, 2011 Issued
Array ( [id] => 10143928 [patent_doc_number] => 09176737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-03 [patent_title] => 'Controlling the execution of adjacent instructions that are dependent upon a same data condition' [patent_app_type] => utility [patent_app_number] => 12/929667 [patent_app_country] => US [patent_app_date] => 2011-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7091 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12929667 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/929667
Controlling the execution of adjacent instructions that are dependent upon a same data condition Feb 6, 2011 Issued
Array ( [id] => 12011676 [patent_doc_number] => 09804995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Computational resource pipelining in general purpose graphics processing unit' [patent_app_type] => utility [patent_app_number] => 13/007333 [patent_app_country] => US [patent_app_date] => 2011-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8513 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13007333 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/007333
Computational resource pipelining in general purpose graphics processing unit Jan 13, 2011 Issued
Array ( [id] => 10098901 [patent_doc_number] => 09135213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Extending a processor system within an integrated circuit and offloading processes to process-specific circuits' [patent_app_type] => utility [patent_app_number] => 13/005962 [patent_app_country] => US [patent_app_date] => 2011-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 12839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13005962 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/005962
Extending a processor system within an integrated circuit and offloading processes to process-specific circuits Jan 12, 2011 Issued
Array ( [id] => 8201764 [patent_doc_number] => 20120124337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'Size mis-match hazard detection' [patent_app_type] => utility [patent_app_number] => 12/926414 [patent_app_country] => US [patent_app_date] => 2010-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4634 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124337.pdf [firstpage_image] =>[orig_patent_app_number] => 12926414 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/926414
Size mis-match hazard detection Nov 15, 2010 Issued
Array ( [id] => 12331653 [patent_doc_number] => 09946545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Buffer store with a main store and and auxiliary store [patent_app_type] => utility [patent_app_number] => 12/926415 [patent_app_country] => US [patent_app_date] => 2010-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3383 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12926415 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/926415
Buffer store with a main store and and auxiliary store Nov 15, 2010 Issued
Array ( [id] => 10157652 [patent_doc_number] => 09189432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Apparatus and method for predicting target storage unit' [patent_app_type] => utility [patent_app_number] => 12/926394 [patent_app_country] => US [patent_app_date] => 2010-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7070 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12926394 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/926394
Apparatus and method for predicting target storage unit Nov 14, 2010 Issued
Array ( [id] => 8201783 [patent_doc_number] => 20120124346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'Decoding conditional program instructions' [patent_app_type] => utility [patent_app_number] => 12/926395 [patent_app_country] => US [patent_app_date] => 2010-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3234 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124346.pdf [firstpage_image] =>[orig_patent_app_number] => 12926395 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/926395
Decoding conditional program instructions Nov 14, 2010 Abandoned
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