Search

Edna Wong

Examiner (ID: 7865, Phone: (571)272-1349 , Office: P/1759 )

Most Active Art Unit
1795
Art Unit(s)
1795, 1751, 1753, 1759, 1102, 1741, 1111
Total Applications
2585
Issued Applications
1631
Pending Applications
215
Abandoned Applications
738

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8201769 [patent_doc_number] => 20120124340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'Retirement serialisation of status register access operations' [patent_app_type] => utility [patent_app_number] => 12/926374 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124340.pdf [firstpage_image] =>[orig_patent_app_number] => 12926374 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/926374
Retirement serialisation of status register access operations Nov 11, 2010 Issued
Array ( [id] => 6166349 [patent_doc_number] => 20110161634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'Processor, co-processor, information processing system, and method for controlling processor, co-processor, and information processing system' [patent_app_type] => utility [patent_app_number] => 12/926350 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 75 [patent_no_of_words] => 16126 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20110161634.pdf [firstpage_image] =>[orig_patent_app_number] => 12926350 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/926350
Processor, co-processor, information processing system, and method for controlling processor, co-processor, and information processing system Nov 11, 2010 Abandoned
Array ( [id] => 6634052 [patent_doc_number] => 20100325399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'VECTOR TEST INSTRUCTION FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 12/873074 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 35520 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0325/20100325399.pdf [firstpage_image] =>[orig_patent_app_number] => 12873074 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/873074
VECTOR TEST INSTRUCTION FOR PROCESSING VECTORS Aug 30, 2010 Abandoned
Array ( [id] => 5940024 [patent_doc_number] => 20110213946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'PARALLEL COMPUTING SYSTEM AND COMMUNICATION CONTROL PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/872338 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12552 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20110213946.pdf [firstpage_image] =>[orig_patent_app_number] => 12872338 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/872338
Parallel computing system and communication control program Aug 30, 2010 Issued
Array ( [id] => 9458523 [patent_doc_number] => 08719550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Reconfigurable processing system including synchronized postprocessing' [patent_app_type] => utility [patent_app_number] => 12/869200 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9092 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12869200 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869200
Reconfigurable processing system including synchronized postprocessing Aug 25, 2010 Issued
Array ( [id] => 5990530 [patent_doc_number] => 20110099354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'Information processing apparatus and instruction decoder for the information processing apparatus' [patent_app_type] => utility [patent_app_number] => 12/805907 [patent_app_country] => US [patent_app_date] => 2010-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8425 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20110099354.pdf [firstpage_image] =>[orig_patent_app_number] => 12805907 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/805907
Single instruction group information processing apparatus for dynamically performing transient processing associated with a repeat instruction Aug 23, 2010 Issued
Array ( [id] => 9986455 [patent_doc_number] => 09032190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Recovering from an error in a fault tolerant computer system' [patent_app_type] => utility [patent_app_number] => 12/859842 [patent_app_country] => US [patent_app_date] => 2010-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3725 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 448 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12859842 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/859842
Recovering from an error in a fault tolerant computer system Aug 19, 2010 Issued
Array ( [id] => 7785795 [patent_doc_number] => 20120047351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'DATA PROCESSING SYSTEM HAVING SELECTIVE REDUNDANCY AND METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 12/858599 [patent_app_country] => US [patent_app_date] => 2010-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20120047351.pdf [firstpage_image] =>[orig_patent_app_number] => 12858599 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/858599
Data processing system having selective redundancy and method therefor Aug 17, 2010 Issued
Array ( [id] => 6031480 [patent_doc_number] => 20110055522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'REQUEST CONTROL DEVICE, REQUEST CONTROL METHOD AND ASSOCIATED PROCESSORS' [patent_app_type] => utility [patent_app_number] => 12/858588 [patent_app_country] => US [patent_app_date] => 2010-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7879 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055522.pdf [firstpage_image] =>[orig_patent_app_number] => 12858588 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/858588
Request control device, request control method and associated processors Aug 17, 2010 Issued
Array ( [id] => 7746852 [patent_doc_number] => 20120023315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'Generating Hardware Events Via the Instruction Stream for Microprocessor Verification' [patent_app_type] => utility [patent_app_number] => 12/843594 [patent_app_country] => US [patent_app_date] => 2010-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5876 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20120023315.pdf [firstpage_image] =>[orig_patent_app_number] => 12843594 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/843594
Generating hardware events via the instruction stream for microprocessor verification Jul 25, 2010 Issued
Array ( [id] => 7671556 [patent_doc_number] => 20110320825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'FUNCTION VIRTUALIZATION FACILITY FOR FUNCTION QUERY OF A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/822358 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 21803 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822358 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822358
Function virtualization facility for function query of a processor Jun 23, 2010 Issued
Array ( [id] => 7582265 [patent_doc_number] => 20110296148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'Transactional Memory System Supporting Unbroken Suspended Execution' [patent_app_type] => utility [patent_app_number] => 12/788351 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11964 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296148.pdf [firstpage_image] =>[orig_patent_app_number] => 12788351 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/788351
Transactional memory system supporting unbroken suspended execution May 26, 2010 Issued
Array ( [id] => 12291213 [patent_doc_number] => 09934079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Fast remote communication and computation between processors using store and load operations on direct core-to-core memory [patent_app_type] => utility [patent_app_number] => 12/789082 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9146 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12789082 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/789082
Fast remote communication and computation between processors using store and load operations on direct core-to-core memory May 26, 2010 Issued
Array ( [id] => 7582257 [patent_doc_number] => 20110296140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'RISC processor register expansion method' [patent_app_type] => utility [patent_app_number] => 12/801131 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3639 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296140.pdf [firstpage_image] =>[orig_patent_app_number] => 12801131 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/801131
RISC processor register expansion method May 24, 2010 Abandoned
Array ( [id] => 8060543 [patent_doc_number] => 20110246748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'Managing Sensor and Actuator Data for a Processor and Service Processor Located on a Common Socket' [patent_app_type] => utility [patent_app_number] => 12/755083 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7897 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246748.pdf [firstpage_image] =>[orig_patent_app_number] => 12755083 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/755083
Managing sensor and actuator data for a processor and service processor located on a common socket Apr 5, 2010 Issued
Array ( [id] => 6167472 [patent_doc_number] => 20110161977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'METHOD AND DEVICE FOR DATA PROCESSING' [patent_app_type] => utility [patent_app_number] => 12/729932 [patent_app_country] => US [patent_app_date] => 2010-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11507 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20110161977.pdf [firstpage_image] =>[orig_patent_app_number] => 12729932 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/729932
METHOD AND DEVICE FOR DATA PROCESSING Mar 22, 2010 Abandoned
Array ( [id] => 6646564 [patent_doc_number] => 20100174868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'Processor device having a sequential data processing unit and an arrangement of data processing elements' [patent_app_type] => utility [patent_app_number] => 12/729090 [patent_app_country] => US [patent_app_date] => 2010-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11438 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20100174868.pdf [firstpage_image] =>[orig_patent_app_number] => 12729090 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/729090
Processor device having a sequential data processing unit and an arrangement of data processing elements Mar 21, 2010 Abandoned
Array ( [id] => 5940013 [patent_doc_number] => 20110213935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'Data processing apparatus and method for switching a workload between first and second processing circuitry' [patent_app_type] => utility [patent_app_number] => 12/659235 [patent_app_country] => US [patent_app_date] => 2010-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13688 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20110213935.pdf [firstpage_image] =>[orig_patent_app_number] => 12659235 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659235
Data processing apparatus and method for switching a workload between first and second processing circuitry Feb 28, 2010 Abandoned
Array ( [id] => 6006035 [patent_doc_number] => 20110119445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'HEAP/STACK GUARD PAGES USING A WAKEUP UNIT' [patent_app_type] => utility [patent_app_number] => 12/696817 [patent_app_country] => US [patent_app_date] => 2010-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6080 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20110119445.pdf [firstpage_image] =>[orig_patent_app_number] => 12696817 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/696817
Heap/stack guard pages using a wakeup unit Jan 28, 2010 Issued
Array ( [id] => 10098693 [patent_doc_number] => 09135005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties' [patent_app_type] => utility [patent_app_number] => 12/695687 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12695687 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/695687
History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties Jan 27, 2010 Issued
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