Search

Edna Wong

Examiner (ID: 7865, Phone: (571)272-1349 , Office: P/1759 )

Most Active Art Unit
1795
Art Unit(s)
1795, 1751, 1753, 1759, 1102, 1741, 1111
Total Applications
2585
Issued Applications
1631
Pending Applications
215
Abandoned Applications
738

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8985101 [patent_doc_number] => 08516231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus' [patent_app_type] => utility [patent_app_number] => 12/695266 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5810 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12695266 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/695266
Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus Jan 27, 2010 Issued
Array ( [id] => 9486475 [patent_doc_number] => 08732437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Low-overhead misalignment and reformatting support for SIMD' [patent_app_type] => utility [patent_app_number] => 12/693634 [patent_app_country] => US [patent_app_date] => 2010-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4908 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12693634 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/693634
Low-overhead misalignment and reformatting support for SIMD Jan 25, 2010 Issued
Array ( [id] => 6554251 [patent_doc_number] => 20100205387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'APPARATUS UTILIZING EFFICIENT HARDWARE IMPLEMENTATION OF SHADOW REGISTERS AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/690719 [patent_app_country] => US [patent_app_date] => 2010-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7964 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20100205387.pdf [firstpage_image] =>[orig_patent_app_number] => 12690719 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/690719
Apparatus utilizing efficient hardware implementation of shadow registers and method thereof Jan 19, 2010 Issued
Array ( [id] => 6234236 [patent_doc_number] => 20100185834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'Data Storing Method and Processor Using the Same' [patent_app_type] => utility [patent_app_number] => 12/688071 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4155 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20100185834.pdf [firstpage_image] =>[orig_patent_app_number] => 12688071 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/688071
Data Storing Method and Processor Using the Same Jan 14, 2010 Abandoned
Array ( [id] => 6181889 [patent_doc_number] => 20110179258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'PRECISE DATA RETURN HANDLING IN SPECULATIVE PROCESSORS' [patent_app_type] => utility [patent_app_number] => 12/688679 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7783 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20110179258.pdf [firstpage_image] =>[orig_patent_app_number] => 12688679 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/688679
Precise data return handling in speculative processors Jan 14, 2010 Issued
Array ( [id] => 6181881 [patent_doc_number] => 20110179254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'LIMITING SPECULATIVE INSTRUCTION FETCHING IN A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/688633 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20110179254.pdf [firstpage_image] =>[orig_patent_app_number] => 12688633 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/688633
LIMITING SPECULATIVE INSTRUCTION FETCHING IN A PROCESSOR Jan 14, 2010 Abandoned
Array ( [id] => 6409255 [patent_doc_number] => 20100180101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'Method for Executing One or More Programs on a Multi-Core Processor and Many-Core Processor' [patent_app_type] => utility [patent_app_number] => 12/685416 [patent_app_country] => US [patent_app_date] => 2010-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20100180101.pdf [firstpage_image] =>[orig_patent_app_number] => 12685416 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/685416
Method for Executing One or More Programs on a Multi-Core Processor and Many-Core Processor Jan 10, 2010 Abandoned
Array ( [id] => 6191219 [patent_doc_number] => 20110173503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'HARDWARE ENABLED PERFORMANCE COUNTERS WITH SUPPORT FOR OPERATING SYSTEM CONTEXT SWITCHING' [patent_app_type] => utility [patent_app_number] => 12/684190 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20110173503.pdf [firstpage_image] =>[orig_patent_app_number] => 12684190 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684190
Hardware enabled performance counters with support for operating system context switching Jan 7, 2010 Issued
Array ( [id] => 6191136 [patent_doc_number] => 20110173420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'PROCESSOR RESUME UNIT' [patent_app_type] => utility [patent_app_number] => 12/684852 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7114 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20110173420.pdf [firstpage_image] =>[orig_patent_app_number] => 12684852 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684852
PROCESSOR RESUME UNIT Jan 7, 2010 Abandoned
Array ( [id] => 5976430 [patent_doc_number] => 20110153991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'DUAL ISSUING OF COMPLEX INSTRUCTION SET INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 12/645716 [patent_app_country] => US [patent_app_date] => 2009-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20110153991.pdf [firstpage_image] =>[orig_patent_app_number] => 12645716 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/645716
Dual issuing of complex instruction set instructions Dec 22, 2009 Issued
Array ( [id] => 12474849 [patent_doc_number] => 09990201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Multiplication instruction for which execution completes without writing a carry flag [patent_app_type] => utility [patent_app_number] => 12/645383 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8081 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12645383 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/645383
Multiplication instruction for which execution completes without writing a carry flag Dec 21, 2009 Issued
Array ( [id] => 9885917 [patent_doc_number] => 08972702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Systems and methods for power management in a high performance computing (HPC) cluster' [patent_app_type] => utility [patent_app_number] => 12/627589 [patent_app_country] => US [patent_app_date] => 2009-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4781 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12627589 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/627589
Systems and methods for power management in a high performance computing (HPC) cluster Nov 29, 2009 Issued
Array ( [id] => 6619612 [patent_doc_number] => 20100064106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'DATA PROCESSOR AND DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/546672 [patent_app_country] => US [patent_app_date] => 2009-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9688 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064106.pdf [firstpage_image] =>[orig_patent_app_number] => 12546672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/546672
DATA PROCESSOR AND DATA PROCESSING SYSTEM Aug 23, 2009 Abandoned
Array ( [id] => 6510357 [patent_doc_number] => 20100011196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Method and program network for exception handling' [patent_app_type] => utility [patent_app_number] => 12/499844 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20100011196.pdf [firstpage_image] =>[orig_patent_app_number] => 12499844 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/499844
Method and program network for exception handling Jul 8, 2009 Abandoned
Array ( [id] => 6262664 [patent_doc_number] => 20100031002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'SIMD MICROPROCESSOR AND OPERATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/495853 [patent_app_country] => US [patent_app_date] => 2009-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5196 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20100031002.pdf [firstpage_image] =>[orig_patent_app_number] => 12495853 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495853
SIMD MICROPROCESSOR AND OPERATION METHOD Jun 30, 2009 Abandoned
Array ( [id] => 6362694 [patent_doc_number] => 20100332792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Integrated Vector-Scalar Processor' [patent_app_type] => utility [patent_app_number] => 12/495246 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7650 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332792.pdf [firstpage_image] =>[orig_patent_app_number] => 12495246 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495246
Integrated Vector-Scalar Processor Jun 29, 2009 Abandoned
Array ( [id] => 10046475 [patent_doc_number] => 09086872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Unpacking packed data in multiple lanes' [patent_app_type] => utility [patent_app_number] => 12/494667 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8815 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12494667 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494667
Unpacking packed data in multiple lanes Jun 29, 2009 Issued
Array ( [id] => 6491381 [patent_doc_number] => 20100042807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'INCREMENT-PROPAGATE AND DECREMENT-PROPAGATE INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 12/495631 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 35180 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20100042807.pdf [firstpage_image] =>[orig_patent_app_number] => 12495631 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495631
Increment-propagate and decrement-propagate instructions for processing vectors Jun 29, 2009 Issued
Array ( [id] => 8775410 [patent_doc_number] => 08429386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Dynamic tag allocation in a multithreaded out-of-order processor' [patent_app_type] => utility [patent_app_number] => 12/494532 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15729 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12494532 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494532
Dynamic tag allocation in a multithreaded out-of-order processor Jun 29, 2009 Issued
Array ( [id] => 6491526 [patent_doc_number] => 20100042817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'SHIFT-IN-RIGHT INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 12/495643 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 34204 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20100042817.pdf [firstpage_image] =>[orig_patent_app_number] => 12495643 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495643
Shift-in-right instructions for processing vectors Jun 29, 2009 Issued
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