Edna Wong

Array ( [id] => 4841581 [patent_doc_number] => 20080282067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'Issue policy control within a multi-threaded in-order superscalar processor' [patent_app_type] => utility [patent_app_number] => 12/078100 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5718 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20080282067.pdf [firstpage_image] =>[orig_patent_app_number] => 12078100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9967816 [patent_doc_number] => 09015451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Processor including a cache and a scratch pad memory and memory control method thereof' [patent_app_type] => utility [patent_app_number] => 12/048658 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12048658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5481835 [patent_doc_number] => 20090204792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'Scalar Processor Instruction Level Parallelism (ILP) Coupled Pair Morph Mechanism' [patent_app_type] => utility [patent_app_number] => 12/030252 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8536 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20090204792.pdf [firstpage_image] =>[orig_patent_app_number] => 12030252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5481834 [patent_doc_number] => 20090204791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'Compound Instruction Group Formation and Execution' [patent_app_type] => utility [patent_app_number] => 12/029830 [patent_app_country] => US [patent_app_date] => 2008-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6348 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20090204791.pdf [firstpage_image] =>[orig_patent_app_number] => 12029830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7706242 [patent_doc_number] => 08090933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Methods computer program products and systems for unifying program event recording for branches and stores in the same dataflow' [patent_app_type] => utility [patent_app_number] => 12/029696 [patent_app_country] => US [patent_app_date] => 2008-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2856 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/090/08090933.pdf [firstpage_image] =>[orig_patent_app_number] => 12029696 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5356549 [patent_doc_number] => 20090187893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'COORDINATING CHORES IN A MULTIPROCESSING ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 12/018060 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20090187893.pdf [firstpage_image] =>[orig_patent_app_number] => 12018060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5411675 [patent_doc_number] => 20090125574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'Software Pipelining On a Network On Chip' [patent_app_type] => utility [patent_app_number] => 11/938376 [patent_app_country] => US [patent_app_date] => 2007-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20090125574.pdf [firstpage_image] =>[orig_patent_app_number] => 11938376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6031479 [patent_doc_number] => 20110055521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'MICROPROCESSOR HAVING AT LEAST ONE APPLICATION SPECIFIC FUNCTIONAL UNIT AND METHOD TO DESIGN SAME' [patent_app_type] => utility [patent_app_number] => 12/311177 [patent_app_country] => US [patent_app_date] => 2007-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3954 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055521.pdf [firstpage_image] =>[orig_patent_app_number] => 12311177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6646736 [patent_doc_number] => 20100174892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'MULTIPROCESSOR SYSTEM AND METHOD FOR SYNCHRONIZING A DEBUGGING PROCESS OF A MULTIPROCESSOR SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/438119 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3105 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20100174892.pdf [firstpage_image] =>[orig_patent_app_number] => 12438119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4761196 [patent_doc_number] => 20080313422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'Enhanced Single Threaded Execution in a Simultaneous Multithreaded Microprocessor' [patent_app_type] => utility [patent_app_number] => 11/763736 [patent_app_country] => US [patent_app_date] => 2007-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11677 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313422.pdf [firstpage_image] =>[orig_patent_app_number] => 11763736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4761199 [patent_doc_number] => 20080313425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'Enhanced Load Lookahead Prefetch in Single Threaded Mode for a Simultaneous Multithreaded Microprocessor' [patent_app_type] => utility [patent_app_number] => 11/763760 [patent_app_country] => US [patent_app_date] => 2007-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313425.pdf [firstpage_image] =>[orig_patent_app_number] => 11763760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4761212 [patent_doc_number] => 20080313438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'Unified Cascaded Delayed Execution Pipeline for Fixed and Floating Point Instructions' [patent_app_type] => utility [patent_app_number] => 11/762824 [patent_app_country] => US [patent_app_date] => 2007-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10092 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313438.pdf [firstpage_image] =>[orig_patent_app_number] => 11762824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7718477 [patent_doc_number] => 08095782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-10 [patent_title] => 'Multiple simultaneous context architecture for rebalancing contexts on multithreaded processing cores upon a context change' [patent_app_type] => utility [patent_app_number] => 11/763371 [patent_app_country] => US [patent_app_date] => 2007-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 12244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/095/08095782.pdf [firstpage_image] =>[orig_patent_app_number] => 11763371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4761216 [patent_doc_number] => 20080313442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'DEBUGGING TECHNIQUES FOR A PROGRAMMABLE INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/762647 [patent_app_country] => US [patent_app_date] => 2007-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3040 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313442.pdf [firstpage_image] =>[orig_patent_app_number] => 11762647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4722363 [patent_doc_number] => 20080244235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'CIRCUIT MARGINALITY VALIDATION TEST FOR AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/694755 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244235.pdf [firstpage_image] =>[orig_patent_app_number] => 11694755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5212098 [patent_doc_number] => 20070250682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Method and apparatus for operating a computer processor array' [patent_app_type] => utility [patent_app_number] => 11/731747 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 17308 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20070250682.pdf [firstpage_image] =>[orig_patent_app_number] => 11731747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4722347 [patent_doc_number] => 20080244224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Scheduling a direct dependent instruction' [patent_app_type] => utility [patent_app_number] => 11/729711 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2687 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244224.pdf [firstpage_image] =>[orig_patent_app_number] => 11729711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4826448 [patent_doc_number] => 20080229312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Processor register architecture' [patent_app_type] => utility [patent_app_number] => 11/717623 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10183 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229312.pdf [firstpage_image] =>[orig_patent_app_number] => 11717623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4700215 [patent_doc_number] => 20080222399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'METHOD FOR THE HANDLING OF MODE-SETTING INSTRUCTIONS IN A MULTITHREADED COMPUTING ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 11/682028 [patent_app_country] => US [patent_app_date] => 2007-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5224 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222399.pdf [firstpage_image] =>[orig_patent_app_number] => 11682028 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5976404 [patent_doc_number] => 20110153980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'MULTI-STAGE RECONFIGURATION DEVICE AND RECONFIGURATION METHOD, LOGIC CIRCUIT CORRECTION DEVICE, AND RECONFIGURABLE MULTI-STAGE LOGIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/294763 [patent_app_country] => US [patent_app_date] => 2007-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 16210 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20110153980.pdf [firstpage_image] =>[orig_patent_app_number] => 12294763 [rel_patent_id] =>[rel_patent_doc_number] =>)