Search

Edna Wong

Examiner (ID: 7865, Phone: (571)272-1349 , Office: P/1759 )

Most Active Art Unit
1795
Art Unit(s)
1795, 1751, 1753, 1759, 1102, 1741, 1111
Total Applications
2585
Issued Applications
1631
Pending Applications
215
Abandoned Applications
738

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4730484 [patent_doc_number] => 20080209190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'PARALLEL PREDICTION OF MULTIPLE BRANCHES' [patent_app_type] => utility [patent_app_number] => 11/680043 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209190.pdf [firstpage_image] =>[orig_patent_app_number] => 11680043 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/680043
PARALLEL PREDICTION OF MULTIPLE BRANCHES Feb 27, 2007 Abandoned
Array ( [id] => 4945479 [patent_doc_number] => 20080082806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Cache controller, microprocessor system, and storage device' [patent_app_type] => utility [patent_app_number] => 11/711233 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6771 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20080082806.pdf [firstpage_image] =>[orig_patent_app_number] => 11711233 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/711233
Cache controller, microprocessor system, and storage device Feb 26, 2007 Abandoned
Array ( [id] => 4815216 [patent_doc_number] => 20080195847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'Aggressive Loop Parallelization using Speculative Execution Mechanisms' [patent_app_type] => utility [patent_app_number] => 11/673905 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20080195847.pdf [firstpage_image] =>[orig_patent_app_number] => 11673905 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673905
Aggressive loop parallelization using speculative execution mechanisms Feb 11, 2007 Issued
Array ( [id] => 5006561 [patent_doc_number] => 20070204134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'Instruction sets for microprocessors' [patent_app_type] => utility [patent_app_number] => 11/704725 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2234 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20070204134.pdf [firstpage_image] =>[orig_patent_app_number] => 11704725 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/704725
Method and apparatus for selecting among a plurality of instruction sets to a microprocessor Feb 8, 2007 Issued
Array ( [id] => 4956492 [patent_doc_number] => 20080189516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'USING IR DROP DATA FOR INSTRUCTION THREAD DIRECTION' [patent_app_type] => utility [patent_app_number] => 11/671613 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6313 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20080189516.pdf [firstpage_image] =>[orig_patent_app_number] => 11671613 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/671613
Using IR drop data for instruction thread direction Feb 5, 2007 Issued
Array ( [id] => 4956493 [patent_doc_number] => 20080189517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'USING TEMPERATURE DATA FOR INSTRUCTION THREAD DIRECTION' [patent_app_type] => utility [patent_app_number] => 11/671640 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6277 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20080189517.pdf [firstpage_image] =>[orig_patent_app_number] => 11671640 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/671640
Using temperature data for instruction thread direction Feb 5, 2007 Issued
Array ( [id] => 4956498 [patent_doc_number] => 20080189522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Method and Apparatus for Enabling Resource Allocation Identification at the Instruction Level in a Processor System' [patent_app_type] => utility [patent_app_number] => 11/671508 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12674 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20080189522.pdf [firstpage_image] =>[orig_patent_app_number] => 11671508 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/671508
Method and apparatus for enabling resource allocation identification at the instruction level in a processor system Feb 5, 2007 Issued
Array ( [id] => 4508227 [patent_doc_number] => 07958342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-07 [patent_title] => 'Methods for optimizing computer system performance counter utilization' [patent_app_type] => utility [patent_app_number] => 11/626833 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958342.pdf [firstpage_image] =>[orig_patent_app_number] => 11626833 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/626833
Methods for optimizing computer system performance counter utilization Jan 23, 2007 Issued
Array ( [id] => 4774107 [patent_doc_number] => 20080059769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'MULTIPLE-CORE PROCESSOR SUPPORTING MULTIPLE INSTRUCTION SET ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 11/468547 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2406 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059769.pdf [firstpage_image] =>[orig_patent_app_number] => 11468547 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/468547
Multiple-core processor supporting multiple instruction set architectures Aug 29, 2006 Issued
Array ( [id] => 4829406 [patent_doc_number] => 20080126472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Computer communication' [patent_app_type] => utility [patent_app_number] => 11/510950 [patent_app_country] => US [patent_app_date] => 2006-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9204 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20080126472.pdf [firstpage_image] =>[orig_patent_app_number] => 11510950 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510950
Computer communication Aug 27, 2006 Abandoned
Array ( [id] => 4735508 [patent_doc_number] => 20080052490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Computational resource array' [patent_app_type] => utility [patent_app_number] => 11/510894 [patent_app_country] => US [patent_app_date] => 2006-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10002 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052490.pdf [firstpage_image] =>[orig_patent_app_number] => 11510894 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510894
Computational resource array Aug 27, 2006 Abandoned
Array ( [id] => 4735543 [patent_doc_number] => 20080052525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Password recovery' [patent_app_type] => utility [patent_app_number] => 11/510922 [patent_app_country] => US [patent_app_date] => 2006-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9557 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052525.pdf [firstpage_image] =>[orig_patent_app_number] => 11510922 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510922
Password recovery Aug 27, 2006 Abandoned
Array ( [id] => 4735447 [patent_doc_number] => 20080052429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Off-board computational resources' [patent_app_type] => utility [patent_app_number] => 11/511190 [patent_app_country] => US [patent_app_date] => 2006-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9101 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052429.pdf [firstpage_image] =>[orig_patent_app_number] => 11511190 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/511190
Off-board computational resources Aug 27, 2006 Abandoned
Array ( [id] => 5641738 [patent_doc_number] => 20060280193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'METHOD AND APPARATUS FOR PERFORMING PACKET CLASSIFICATION FOR POLICY-BASED PACKET ROUTING' [patent_app_type] => utility [patent_app_number] => 11/466395 [patent_app_country] => US [patent_app_date] => 2006-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 28922 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20060280193.pdf [firstpage_image] =>[orig_patent_app_number] => 11466395 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/466395
METHOD AND APPARATUS FOR PERFORMING PACKET CLASSIFICATION FOR POLICY-BASED PACKET ROUTING Aug 21, 2006 Abandoned
Array ( [id] => 10885502 [patent_doc_number] => 08909905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Method for performing plurality of bit operations and a device having plurality of bit operations capabilities' [patent_app_type] => utility [patent_app_number] => 12/377351 [patent_app_country] => US [patent_app_date] => 2006-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12377351 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/377351
Method for performing plurality of bit operations and a device having plurality of bit operations capabilities Aug 17, 2006 Issued
Array ( [id] => 8149264 [patent_doc_number] => 08166283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Generator of a signal with an adjustable waveform' [patent_app_type] => utility [patent_app_number] => 11/502343 [patent_app_country] => US [patent_app_date] => 2006-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 5838 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166283.pdf [firstpage_image] =>[orig_patent_app_number] => 11502343 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/502343
Generator of a signal with an adjustable waveform Aug 9, 2006 Issued
Array ( [id] => 4653319 [patent_doc_number] => 20080040576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Associate Cached Branch Information with the Last Granularity of Branch instruction in Variable Length instruction Set' [patent_app_type] => utility [patent_app_number] => 11/463370 [patent_app_country] => US [patent_app_date] => 2006-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4160 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040576.pdf [firstpage_image] =>[orig_patent_app_number] => 11463370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463370
Associate Cached Branch Information with the Last Granularity of Branch instruction in Variable Length instruction Set Aug 8, 2006 Abandoned
Array ( [id] => 5610253 [patent_doc_number] => 20060271769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Selectively deferring instructions issued in program order utilizing a checkpoint and instruction deferral scheme' [patent_app_type] => utility [patent_app_number] => 11/495450 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3077 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20060271769.pdf [firstpage_image] =>[orig_patent_app_number] => 11495450 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/495450
Selectively deferring instructions issued in program order utilizing a checkpoint and instruction deferral scheme Jul 27, 2006 Abandoned
Array ( [id] => 8472677 [patent_doc_number] => 08301870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Method and apparatus for fast synchronization and out-of-order execution of instructions in a meta-program based computing system' [patent_app_type] => utility [patent_app_number] => 11/493665 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7446 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11493665 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/493665
Method and apparatus for fast synchronization and out-of-order execution of instructions in a meta-program based computing system Jul 26, 2006 Issued
Array ( [id] => 5206595 [patent_doc_number] => 20070028077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Pipeline processor, and method for automatically designing a pipeline processor' [patent_app_type] => utility [patent_app_number] => 11/492937 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20070028077.pdf [firstpage_image] =>[orig_patent_app_number] => 11492937 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/492937
Pipeline processor, and method for automatically designing a pipeline processor Jul 25, 2006 Abandoned
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