Search

Edna Wong

Examiner (ID: 7865, Phone: (571)272-1349 , Office: P/1759 )

Most Active Art Unit
1795
Art Unit(s)
1795, 1751, 1753, 1759, 1102, 1741, 1111
Total Applications
2585
Issued Applications
1631
Pending Applications
215
Abandoned Applications
738

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5017645 [patent_doc_number] => 20070260854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'PRE-DECODING VARIABLE LENGTH INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 11/381545 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2959 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20070260854.pdf [firstpage_image] =>[orig_patent_app_number] => 11381545 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/381545
Pre-decoding variable length instructions May 3, 2006 Issued
Array ( [id] => 5734635 [patent_doc_number] => 20060259752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Stateless Branch Prediction Scheme for VLIW Processor' [patent_app_type] => utility [patent_app_number] => 11/381614 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3616 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259752.pdf [firstpage_image] =>[orig_patent_app_number] => 11381614 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/381614
Stateless Branch Prediction Scheme for VLIW Processor May 3, 2006 Abandoned
Array ( [id] => 7684036 [patent_doc_number] => 20100122105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'RECONFIGURABLE INSTRUCTION CELL ARRAY' [patent_app_type] => utility [patent_app_number] => 11/919270 [patent_app_country] => US [patent_app_date] => 2006-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11682 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 40 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122105.pdf [firstpage_image] =>[orig_patent_app_number] => 11919270 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/919270
RECONFIGURABLE INSTRUCTION CELL ARRAY Apr 27, 2006 Abandoned
Array ( [id] => 5789395 [patent_doc_number] => 20060206869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'METHODS AND SYSTEMS FOR DEVELOPING DATA FLOW PROGRAMS' [patent_app_type] => utility [patent_app_number] => 11/379684 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 12792 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20060206869.pdf [firstpage_image] =>[orig_patent_app_number] => 11379684 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/379684
METHODS AND SYSTEMS FOR DEVELOPING DATA FLOW PROGRAMS Apr 20, 2006 Abandoned
Array ( [id] => 5510547 [patent_doc_number] => 20090083754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'IMPLEMENTATION OF MULTI-TASKING ON A DIGITAL SIGNAL PROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/911873 [patent_app_country] => US [patent_app_date] => 2006-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3590 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20090083754.pdf [firstpage_image] =>[orig_patent_app_number] => 11911873 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/911873
Implementation of multi-tasking on a digital signal processor with a hardware stack Apr 6, 2006 Issued
Array ( [id] => 5755990 [patent_doc_number] => 20060225139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/393833 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10210 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20060225139.pdf [firstpage_image] =>[orig_patent_app_number] => 11393833 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/393833
Semiconductor integrated circuit Mar 30, 2006 Abandoned
Array ( [id] => 5137447 [patent_doc_number] => 20070079076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Data processing apparatus and data processing method for performing pipeline processing based on RISC architecture' [patent_app_type] => utility [patent_app_number] => 11/392641 [patent_app_country] => US [patent_app_date] => 2006-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6302 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20070079076.pdf [firstpage_image] =>[orig_patent_app_number] => 11392641 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/392641
Data processing apparatus and data processing method for performing pipeline processing based on RISC architecture Mar 29, 2006 Abandoned
Array ( [id] => 5064820 [patent_doc_number] => 20070226462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Data processor having dynamic control of instruction prefetch buffer depth and method therefor' [patent_app_type] => utility [patent_app_number] => 11/385463 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3832 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226462.pdf [firstpage_image] =>[orig_patent_app_number] => 11385463 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/385463
Data processor having dynamic control of instruction prefetch buffer depth and method therefor Mar 20, 2006 Issued
Array ( [id] => 10879357 [patent_doc_number] => 08904155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Representing loop branches in a branch history register with multiple bits' [patent_app_type] => utility [patent_app_number] => 11/378712 [patent_app_country] => US [patent_app_date] => 2006-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4630 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11378712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/378712
Representing loop branches in a branch history register with multiple bits Mar 16, 2006 Issued
Array ( [id] => 5852884 [patent_doc_number] => 20060236075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'SIMD microprocessor and data processing method' [patent_app_type] => utility [patent_app_number] => 11/377521 [patent_app_country] => US [patent_app_date] => 2006-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 19074 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20060236075.pdf [firstpage_image] =>[orig_patent_app_number] => 11377521 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/377521
SIMD microprocessor and data processing method Mar 16, 2006 Abandoned
11/378992 Method, system, and apparatus for supporting switching of threads in a pipelined design Mar 16, 2006 Abandoned
Array ( [id] => 5024732 [patent_doc_number] => 20070150699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Firm partitioning in a system with a point-to-point interconnect' [patent_app_type] => utility [patent_app_number] => 11/321213 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2785 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20070150699.pdf [firstpage_image] =>[orig_patent_app_number] => 11321213 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/321213
Firm partitioning in a system with a point-to-point interconnect Dec 27, 2005 Abandoned
Array ( [id] => 4616531 [patent_doc_number] => 07991984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'System and method for executing loops in a processor' [patent_app_type] => utility [patent_app_number] => 11/317361 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/991/07991984.pdf [firstpage_image] =>[orig_patent_app_number] => 11317361 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/317361
System and method for executing loops in a processor Dec 22, 2005 Issued
Array ( [id] => 593604 [patent_doc_number] => 07461243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Deferred branch history update scheme' [patent_app_type] => utility [patent_app_number] => 11/316722 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/461/07461243.pdf [firstpage_image] =>[orig_patent_app_number] => 11316722 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/316722
Deferred branch history update scheme Dec 21, 2005 Issued
Array ( [id] => 5597695 [patent_doc_number] => 20060161613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Method and apparatus for arithmatic operation of processor' [patent_app_type] => utility [patent_app_number] => 11/317108 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3800 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20060161613.pdf [firstpage_image] =>[orig_patent_app_number] => 11317108 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/317108
Method and apparatus for arithmatic operation of processor Dec 21, 2005 Abandoned
Array ( [id] => 5024904 [patent_doc_number] => 20070150871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Autonomically adjusting the collection of performance data from a call stack' [patent_app_type] => utility [patent_app_number] => 11/316287 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5675 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20070150871.pdf [firstpage_image] =>[orig_patent_app_number] => 11316287 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/316287
Autonomically adjusting the collection of performance data from a call stack Dec 21, 2005 Abandoned
Array ( [id] => 5150544 [patent_doc_number] => 20070050604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Fetch rerouting in response to an execution-based optimization profile' [patent_app_type] => utility [patent_app_number] => 11/291503 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 13838 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20070050604.pdf [firstpage_image] =>[orig_patent_app_number] => 11291503 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/291503
Fetch rerouting in response to an execution-based optimization profile Nov 29, 2005 Abandoned
Array ( [id] => 5081504 [patent_doc_number] => 20070124728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Passing work between threads' [patent_app_type] => utility [patent_app_number] => 11/288819 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8528 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20070124728.pdf [firstpage_image] =>[orig_patent_app_number] => 11288819 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/288819
Passing work between threads Nov 27, 2005 Abandoned
Array ( [id] => 5867124 [patent_doc_number] => 20060101255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Method and apparatus for clearing hazards using jump instructions' [patent_app_type] => utility [patent_app_number] => 11/284069 [patent_app_country] => US [patent_app_date] => 2005-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5989 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101255.pdf [firstpage_image] =>[orig_patent_app_number] => 11284069 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/284069
Method and apparatus for clearing hazards using jump instructions Nov 20, 2005 Issued
Array ( [id] => 5206605 [patent_doc_number] => 20070028087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Method and system for reducing instruction storage space for a processor integrated in a network adapter chip' [patent_app_type] => utility [patent_app_number] => 11/273281 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15877 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20070028087.pdf [firstpage_image] =>[orig_patent_app_number] => 11273281 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/273281
Method and system for reducing instruction storage space for a processor integrated in a network adapter chip Nov 13, 2005 Issued
Menu