Search

Edna Wong

Examiner (ID: 7865, Phone: (571)272-1349 , Office: P/1759 )

Most Active Art Unit
1795
Art Unit(s)
1795, 1751, 1753, 1759, 1102, 1741, 1111
Total Applications
2585
Issued Applications
1631
Pending Applications
215
Abandoned Applications
738

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6962343 [patent_doc_number] => 20050216704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Device and method for managing a microprocessor instruction set' [patent_app_type] => utility [patent_app_number] => 11/083346 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3365 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216704.pdf [firstpage_image] =>[orig_patent_app_number] => 11083346 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/083346
Device and method for managing a microprocessor instruction set Mar 16, 2005 Abandoned
Array ( [id] => 146585 [patent_doc_number] => 07689813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor' [patent_app_type] => utility [patent_app_number] => 11/083263 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4364 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689813.pdf [firstpage_image] =>[orig_patent_app_number] => 11083263 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/083263
Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor Mar 15, 2005 Issued
Array ( [id] => 5789021 [patent_doc_number] => 20060206732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Methods and apparatus for improving processing performance using instruction dependency check depth' [patent_app_type] => utility [patent_app_number] => 11/079566 [patent_app_country] => US [patent_app_date] => 2005-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7457 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20060206732.pdf [firstpage_image] =>[orig_patent_app_number] => 11079566 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/079566
Methods and apparatus for improving processing performance using instruction dependency check depth Mar 13, 2005 Abandoned
Array ( [id] => 283945 [patent_doc_number] => 07555630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit' [patent_app_type] => utility [patent_app_number] => 11/018579 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4922 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/555/07555630.pdf [firstpage_image] =>[orig_patent_app_number] => 11018579 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/018579
Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit Dec 20, 2004 Issued
Array ( [id] => 5156088 [patent_doc_number] => 20070038971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Processing device with reconfigurable circuit, integrated circuit device and processing method using these devices' [patent_app_type] => utility [patent_app_number] => 10/573970 [patent_app_country] => US [patent_app_date] => 2004-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 12897 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20070038971.pdf [firstpage_image] =>[orig_patent_app_number] => 10573970 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/573970
Processing device with reconfigurable circuit, integrated circuit device and processing method using these devices Jul 8, 2004 Abandoned
Array ( [id] => 10003001 [patent_doc_number] => 09047094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor' [patent_app_type] => utility [patent_app_number] => 10/813615 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4829 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10813615 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/813615
Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor Mar 30, 2004 Issued
Array ( [id] => 8120099 [patent_doc_number] => 08161270 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-17 [patent_title] => 'Packet data modification processor' [patent_app_type] => utility [patent_app_number] => 10/814556 [patent_app_country] => US [patent_app_date] => 2004-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 14267 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161270.pdf [firstpage_image] =>[orig_patent_app_number] => 10814556 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/814556
Packet data modification processor Mar 29, 2004 Issued
Array ( [id] => 7177873 [patent_doc_number] => 20050204120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Effective delayed, minimized switching, BTB write via recent entry queue that has the ability to delay decode' [patent_app_type] => utility [patent_app_number] => 10/796426 [patent_app_country] => US [patent_app_date] => 2004-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4729 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20050204120.pdf [firstpage_image] =>[orig_patent_app_number] => 10796426 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796426
Method, system and program product for pipelined processor having a branch target buffer (BTB) table with a recent entry queue in parallel with the BTB table Mar 8, 2004 Issued
Array ( [id] => 6946877 [patent_doc_number] => 20050198555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Incorporating instruction reissue in an instruction sampling mechanism' [patent_app_type] => utility [patent_app_number] => 10/792441 [patent_app_country] => US [patent_app_date] => 2004-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2780 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20050198555.pdf [firstpage_image] =>[orig_patent_app_number] => 10792441 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/792441
Incorporating instruction reissue in an instruction sampling mechanism Mar 2, 2004 Abandoned
Array ( [id] => 7052464 [patent_doc_number] => 20050188183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Digital signal processor having data address generator with speculative register file' [patent_app_type] => utility [patent_app_number] => 10/786838 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4348 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20050188183.pdf [firstpage_image] =>[orig_patent_app_number] => 10786838 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/786838
Digital signal processor having data address generator with speculative register file Feb 24, 2004 Abandoned
Array ( [id] => 6941293 [patent_doc_number] => 20050114856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Multithreaded processor and method for switching threads' [patent_app_type] => utility [patent_app_number] => 10/717747 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2827 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20050114856.pdf [firstpage_image] =>[orig_patent_app_number] => 10717747 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/717747
Multithreaded processor and method for switching threads by swapping instructions between buffers while pausing execution Nov 19, 2003 Issued
Array ( [id] => 8158153 [patent_doc_number] => 08171261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Method and system for accessing memory in parallel computing using load fencing instructions' [patent_app_type] => utility [patent_app_number] => 10/654573 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5154 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/171/08171261.pdf [firstpage_image] =>[orig_patent_app_number] => 10654573 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/654573
Method and system for accessing memory in parallel computing using load fencing instructions Sep 1, 2003 Issued
Array ( [id] => 5846790 [patent_doc_number] => 20060123152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Inter-processor communication system for communication between processors' [patent_app_type] => utility [patent_app_number] => 10/521881 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5391 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20060123152.pdf [firstpage_image] =>[orig_patent_app_number] => 10521881 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/521881
Inter-processor communication system for communication between processors Jul 15, 2003 Abandoned
Array ( [id] => 4589517 [patent_doc_number] => 07861061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Processor instruction including option bits encoding which instructions of an instruction packet to execute' [patent_app_type] => utility [patent_app_number] => 10/444932 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5680 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/861/07861061.pdf [firstpage_image] =>[orig_patent_app_number] => 10444932 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/444932
Processor instruction including option bits encoding which instructions of an instruction packet to execute May 22, 2003 Issued
Array ( [id] => 7100336 [patent_doc_number] => 20050132170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Multi-issue processor' [patent_app_type] => utility [patent_app_number] => 10/511512 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3341 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132170.pdf [firstpage_image] =>[orig_patent_app_number] => 10511512 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/511512
Register systems and methods for a multi-issue processor Mar 31, 2003 Issued
Array ( [id] => 5722434 [patent_doc_number] => 20060075211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Method and device for data processing' [patent_app_type] => utility [patent_app_number] => 10/508559 [patent_app_country] => US [patent_app_date] => 2003-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10819 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 29 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20060075211.pdf [firstpage_image] =>[orig_patent_app_number] => 10508559 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/508559
Method and device for data processing Mar 20, 2003 Abandoned
Array ( [id] => 7473991 [patent_doc_number] => 20040054873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Indirect indexing instructions' [patent_app_type] => new [patent_app_number] => 10/245106 [patent_app_country] => US [patent_app_date] => 2002-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3482 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20040054873.pdf [firstpage_image] =>[orig_patent_app_number] => 10245106 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/245106
Indirect indexing instructions Sep 16, 2002 Issued
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