Search

Edward Chin

Examiner (ID: 17638)

Most Active Art Unit
2813
Art Unit(s)
2893, 2821, 2813
Total Applications
838
Issued Applications
672
Pending Applications
94
Abandoned Applications
93

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16578741 [patent_doc_number] => 20210013142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE USING GANGED CONDUCTIVE CONNECTIVE ASSEMBLY AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/035999 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5915 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035999 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/035999
METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE USING GANGED CONDUCTIVE CONNECTIVE ASSEMBLY AND STRUCTURE Sep 28, 2020 Abandoned
Array ( [id] => 18061737 [patent_doc_number] => 20220392824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => HEAT DISSIPATION SHEET, HEAT DISSIPATION SHEET LAYERED BODY, STRUCTURE, AND METHOD FOR DISSIPATING HEAT FROM HEAT-GENERATING ELEMENT [patent_app_type] => utility [patent_app_number] => 17/762235 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17762235 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/762235
HEAT DISSIPATION SHEET, HEAT DISSIPATION SHEET LAYERED BODY, STRUCTURE, AND METHOD FOR DISSIPATING HEAT FROM HEAT-GENERATING ELEMENT Sep 23, 2020 Abandoned
Array ( [id] => 17486290 [patent_doc_number] => 20220093794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => VERTICAL TRANSISTOR FLOATING BODY ONE TRANSISTOR DRAM MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/026199 [patent_app_country] => US [patent_app_date] => 2020-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026199 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026199
Vertical transistor floating body one transistor DRAM memory cell Sep 18, 2020 Issued
Array ( [id] => 20482731 [patent_doc_number] => 12531208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Low temperature plasma enhanced chemical vapor deposition process including preheated showerhead [patent_app_type] => utility [patent_app_number] => 17/761951 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2253 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17761951 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/761951
Low temperature plasma enhanced chemical vapor deposition process including preheated showerhead Sep 15, 2020 Issued
Array ( [id] => 16541434 [patent_doc_number] => 20200407847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => METHOD AND APPARATUS FOR PROVIDING STATION TO STATION UNIFORMITY [patent_app_type] => utility [patent_app_number] => 17/020001 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020001 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/020001
Method and apparatus for providing station to station uniformity Sep 13, 2020 Issued
Array ( [id] => 18315752 [patent_doc_number] => 11629826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => LED lamp [patent_app_type] => utility [patent_app_number] => 17/008007 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 63 [patent_no_of_words] => 5649 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008007
LED lamp Aug 30, 2020 Issued
Array ( [id] => 17448428 [patent_doc_number] => 20220068933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => GATE DIELECTRIC REPAIR ON THREE-NODE ACCESS DEVICE FORMATION FOR VERTICAL THREE-DIMENSIONAL (3D) MEMORY [patent_app_type] => utility [patent_app_number] => 17/005862 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17005862 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/005862
Gate dielectric repair on three-node access device formation for vertical three-dimensional (3D) memory Aug 27, 2020 Issued
Array ( [id] => 16677536 [patent_doc_number] => 20210066302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/003054 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003054 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003054
Memory device having 2-transistor vertical memory cell and shield structures Aug 25, 2020 Issued
Array ( [id] => 18403720 [patent_doc_number] => 11665880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Memory device having 2-transistor vertical memory cell and a common plate [patent_app_type] => utility [patent_app_number] => 17/003037 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 17217 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003037
Memory device having 2-transistor vertical memory cell and a common plate Aug 25, 2020 Issued
Array ( [id] => 17941792 [patent_doc_number] => 11476252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Memory device having 2-transistor vertical memory cell and shared channel region [patent_app_type] => utility [patent_app_number] => 17/003019 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003019
Memory device having 2-transistor vertical memory cell and shared channel region Aug 25, 2020 Issued
Array ( [id] => 16677430 [patent_doc_number] => 20210066196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND A COMMON PLATE [patent_app_type] => utility [patent_app_number] => 17/003065 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003065 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003065
Memory device having 2-transistor vertical memory cell and a common plate Aug 25, 2020 Issued
Array ( [id] => 17448419 [patent_doc_number] => 20220068924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => MEMORY DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/002765 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002765 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/002765
Memory device and method of forming the same Aug 24, 2020 Issued
Array ( [id] => 17417301 [patent_doc_number] => 20220052205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => STRUCTURE WITH POLYCRYSTALLINE ACTIVE REGION FILL SHAPE(S), AND RELATED METHOD [patent_app_type] => utility [patent_app_number] => 16/992440 [patent_app_country] => US [patent_app_date] => 2020-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16992440 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/992440
Structure with polycrystalline active region fill shape(s), and related method Aug 12, 2020 Issued
Array ( [id] => 17852353 [patent_doc_number] => 20220282395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SiC SUBSTRATE, SiC EPITAXIAL SUBSTRATE, SiC INGOT AND PRODUCTION METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/632498 [patent_app_country] => US [patent_app_date] => 2020-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17632498 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/632498
SiC substrate, SiC epitaxial substrate, SiC ingot and production methods thereof Aug 4, 2020 Issued
Array ( [id] => 17493650 [patent_doc_number] => 11282968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Device structure for increasing coupling ratio of body-tied fin structure flash memory cell [patent_app_type] => utility [patent_app_number] => 16/943993 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2944 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943993 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/943993
Device structure for increasing coupling ratio of body-tied fin structure flash memory cell Jul 29, 2020 Issued
Array ( [id] => 17389480 [patent_doc_number] => 20220037332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => STACKED CAPACITOR WITH HORIZONTAL AND VERTICAL FIN STRUCTURES AND METHOD FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/941490 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941490 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941490
Stacked capacitor with horizontal and vertical fin structures and method for making the same Jul 27, 2020 Issued
Array ( [id] => 17115725 [patent_doc_number] => 20210296322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/935848 [patent_app_country] => US [patent_app_date] => 2020-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16935848 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/935848
Semiconductor device and method for fabricating the same Jul 21, 2020 Issued
Array ( [id] => 16398555 [patent_doc_number] => 20200339413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => MEMS PACKAGE WITH ROUGHEND INTERFACE [patent_app_type] => utility [patent_app_number] => 16/927223 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927223 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927223
MEMS package with roughend interface Jul 12, 2020 Issued
Array ( [id] => 16625008 [patent_doc_number] => 20210043661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => POLISHING SLURRY, METHOD FOR MANUFACTURING A DISPLAY DEVICE USING THE SAME AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/927327 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927327 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927327
Polishing slurry, method for manufacturing a display device using the same and display device Jul 12, 2020 Issued
Array ( [id] => 17758167 [patent_doc_number] => 11398466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Semiconductor integrated circuit device [patent_app_type] => utility [patent_app_number] => 16/918852 [patent_app_country] => US [patent_app_date] => 2020-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 45 [patent_no_of_words] => 11502 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16918852 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/918852
Semiconductor integrated circuit device Jun 30, 2020 Issued
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