Edward Chin

Array ( [id] => 16796134 [patent_doc_number] => 20210125951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => INTEGRATED DEVICE COMPRISING INTERCONNECT STRUCTURES HAVING AN INNER INTERCONNECT, A DIELECTRIC LAYER AND A CONDUCTIVE LAYER [patent_app_type] => utility [patent_app_number] => 16/665883 [patent_app_country] => US [patent_app_date] => 2019-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16665883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17224778 [patent_doc_number] => 11177288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Display device comprising a plurality of thin film transistors and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/661760 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 13708 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15841437 [patent_doc_number] => 20200136001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => LED Light Source [patent_app_type] => utility [patent_app_number] => 16/661821 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17716580 [patent_doc_number] => 11380578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Formation of angled gratings [patent_app_type] => utility [patent_app_number] => 16/656798 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 33 [patent_no_of_words] => 11493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16656798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15462457 [patent_doc_number] => 20200044053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => NANOSHEET TRANSITOR WITH OPTIMIZED JUNCTION AND CLADDING DEFECTIVITY CONTROL [patent_app_type] => utility [patent_app_number] => 16/600050 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16600050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15461819 [patent_doc_number] => 20200043734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => SYSTEMS AND METHODS FOR MATERIAL BREAKTHROUGH [patent_app_type] => utility [patent_app_number] => 16/599447 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12838 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15462477 [patent_doc_number] => 20200044063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => VERTICAL TUNNEL FIELD EFFECT TRANSISTOR (FET) [patent_app_type] => utility [patent_app_number] => 16/594404 [patent_app_country] => US [patent_app_date] => 2019-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16594404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15332535 [patent_doc_number] => 20200006597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => GROWTH OF CUBIC CRYSTALLINE PHASE STRUCTURE ON SILICON SUBSTRATES AND DEVICES COMPRISING THE CUBIC CRYSTALLINE PHASE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/567535 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15300503 [patent_doc_number] => 20190393387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/564556 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16774039 [patent_doc_number] => 10985160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Semiconductor structures and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/562650 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562650 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15922229 [patent_doc_number] => 10658363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Cut inside replacement metal gate trench to mitigate N-P proximity effect [patent_app_type] => utility [patent_app_number] => 16/562481 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2708 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19943641 [patent_doc_number] => 12315777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Microelectronics package comprising a package-on-package (POP) architecture with inkjet barrier material for controlling bondline thickness and POP adhesive keep out zone [patent_app_type] => utility [patent_app_number] => 16/557784 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 1105 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16677540 [patent_doc_number] => 20210066306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => ARRAY OF CAPACITORS, AN ARRAY OF MEMORY CELLS, A METHOD OF FORMING AN ARRAY OF CAPACITORS, AND A METHOD OF FORMING AN ARRAY OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/550917 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17196189 [patent_doc_number] => 11164956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Capping layer for gate electrodes [patent_app_type] => utility [patent_app_number] => 16/548918 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548918 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17769233 [patent_doc_number] => 11401158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Sensor packages [patent_app_type] => utility [patent_app_number] => 16/549003 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3739 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15323663 [patent_doc_number] => 20200002161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => METHOD OF FORMING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/544234 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16544234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16675340 [patent_doc_number] => 20210064104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => WIRING STRUCTURE, PREPARATION METHOD THEREOF, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/643919 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16643919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17063284 [patent_doc_number] => 11107897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Methods of forming semiconductor devices and FinFET devices having shielding layers [patent_app_type] => utility [patent_app_number] => 16/524137 [patent_app_country] => US [patent_app_date] => 2019-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4241 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16524137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16653418 [patent_doc_number] => 10930611 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-23 [patent_title] => Solder joints for board level reliability [patent_app_type] => utility [patent_app_number] => 16/523950 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3844 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16896713 [patent_doc_number] => 11038277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => High impedance surface (HIS) enhanced by discrete passives [patent_app_type] => utility [patent_app_number] => 16/521477 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5805 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521477 [rel_patent_id] =>[rel_patent_doc_number] =>)