
Edward Chin
Examiner (ID: 17638)
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2893, 2821, 2813 |
| Total Applications | 838 |
| Issued Applications | 672 |
| Pending Applications | 94 |
| Abandoned Applications | 93 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19132788
[patent_doc_number] => 20240138141
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-25
[patent_title] => VERTICAL NON-VOLATILE MEMORY DEVICES HAVING A MULTI-STACK STRUCTURE WITH ENHANCED PHOTOLITHOGRAPHIC ALIGNMENT CHARACTERISTICS
[patent_app_type] => utility
[patent_app_number] => 18/402144
[patent_app_country] => US
[patent_app_date] => 2024-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11299
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402144
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/402144 | Vertical non-volatile memory devices having a multi-stack structure with enhanced photolithographic alignment characteristics | Jan 1, 2024 | Issued |
Array
(
[id] => 20229302
[patent_doc_number] => 12417958
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-16
[patent_title] => Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone
[patent_app_type] => utility
[patent_app_number] => 18/399205
[patent_app_country] => US
[patent_app_date] => 2023-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 1081
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399205
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/399205 | Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone | Dec 27, 2023 | Issued |
Array
(
[id] => 19118363
[patent_doc_number] => 20240130113
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => SEMICONDUCTOR DEVICE INCLUDING INTEGRATED CAPACITOR AND VERTICAL CHANNEL TRANSISTOR AND METHODS OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/395793
[patent_app_country] => US
[patent_app_date] => 2023-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12011
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395793
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/395793 | Semiconductor device including integrated capacitor and vertical channel transistor and methods of forming the same | Dec 25, 2023 | Issued |
Array
(
[id] => 19465854
[patent_doc_number] => 20240319524
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => Controlling the charge state of a crystal defect
[patent_app_type] => utility
[patent_app_number] => 18/542901
[patent_app_country] => US
[patent_app_date] => 2023-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5611
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18542901
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/542901 | Controlling the charge state of a crystal defect | Dec 17, 2023 | Pending |
Array
(
[id] => 19390975
[patent_doc_number] => 20240280845
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => Resonant cavity with piezoelectric tuning
[patent_app_type] => utility
[patent_app_number] => 18/542868
[patent_app_country] => US
[patent_app_date] => 2023-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5636
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18542868
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/542868 | Resonant cavity with piezoelectric tuning | Dec 17, 2023 | Pending |
Array
(
[id] => 19073314
[patent_doc_number] => 20240107740
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-28
[patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
[patent_app_type] => utility
[patent_app_number] => 18/531765
[patent_app_country] => US
[patent_app_date] => 2023-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10428
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18531765
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/531765 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME | Dec 6, 2023 | Pending |
Array
(
[id] => 19269669
[patent_doc_number] => 20240213374
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => PANEL STRUCTURE AND PREPARING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/522302
[patent_app_country] => US
[patent_app_date] => 2023-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4195
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522302
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/522302 | PANEL STRUCTURE AND PREPARING METHOD THEREOF | Nov 28, 2023 | Pending |
Array
(
[id] => 20028870
[patent_doc_number] => 20250167092
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-22
[patent_title] => ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/518322
[patent_app_country] => US
[patent_app_date] => 2023-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4245
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518322
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/518322 | ELECTRONIC DEVICE | Nov 21, 2023 | Pending |
Array
(
[id] => 19038475
[patent_doc_number] => 20240088290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/506567
[patent_app_country] => US
[patent_app_date] => 2023-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8457
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18506567
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/506567 | Semiconductor component and manufacturing method thereof | Nov 9, 2023 | Issued |
Array
(
[id] => 19255258
[patent_doc_number] => 20240206255
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-20
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/388119
[patent_app_country] => US
[patent_app_date] => 2023-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20094
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18388119
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/388119 | DISPLAY DEVICE | Nov 7, 2023 | Pending |
Array
(
[id] => 19146206
[patent_doc_number] => 20240145235
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-02
[patent_title] => SIN GAP FILL VIA NUCLEATION INHIBITION
[patent_app_type] => utility
[patent_app_number] => 18/495094
[patent_app_country] => US
[patent_app_date] => 2023-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6541
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18495094
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/495094 | SIN GAP FILL VIA NUCLEATION INHIBITION | Oct 25, 2023 | Pending |
Array
(
[id] => 19698453
[patent_doc_number] => 20250016998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-09
[patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/382669
[patent_app_country] => US
[patent_app_date] => 2023-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7309
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18382669
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/382669 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME | Oct 22, 2023 | Pending |
Array
(
[id] => 19634711
[patent_doc_number] => 20240413160
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => CELL ARCHITECTURE WITH IMPROVED BACKSIDE POWER RAIL THROUGH ENGINEERING CHANGE ORDER
[patent_app_type] => utility
[patent_app_number] => 18/382301
[patent_app_country] => US
[patent_app_date] => 2023-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6756
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18382301
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/382301 | CELL ARCHITECTURE WITH IMPROVED BACKSIDE POWER RAIL THROUGH ENGINEERING CHANGE ORDER | Oct 19, 2023 | Pending |
Array
(
[id] => 19988692
[patent_doc_number] => 20250126914
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-17
[patent_title] => IMAGE SENSORS AND METHODS OF MANUFACTURING THEM
[patent_app_type] => utility
[patent_app_number] => 18/487223
[patent_app_country] => US
[patent_app_date] => 2023-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2219
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18487223
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/487223 | IMAGE SENSORS AND METHODS OF MANUFACTURING THEM | Oct 15, 2023 | Pending |
Array
(
[id] => 19116331
[patent_doc_number] => 20240128081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => FILM FORMING METHOD AND FILM FORMING APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/481492
[patent_app_country] => US
[patent_app_date] => 2023-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7761
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18481492
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/481492 | FILM FORMING METHOD AND FILM FORMING APPARATUS | Oct 4, 2023 | Pending |
Array
(
[id] => 19881226
[patent_doc_number] => 20250113483
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-03
[patent_title] => ANTIFUSES CAPABLE OF FORMING LOCALIZED CONDUCTIVE LINKS
[patent_app_type] => utility
[patent_app_number] => 18/479816
[patent_app_country] => US
[patent_app_date] => 2023-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5883
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18479816
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/479816 | ANTIFUSES CAPABLE OF FORMING LOCALIZED CONDUCTIVE LINKS | Oct 1, 2023 | Pending |
Array
(
[id] => 19101193
[patent_doc_number] => 20240120421
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-11
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/479428
[patent_app_country] => US
[patent_app_date] => 2023-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12590
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18479428
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/479428 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | Oct 1, 2023 | Pending |
Array
(
[id] => 19980255
[patent_doc_number] => 12347743
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-01
[patent_title] => Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone
[patent_app_type] => utility
[patent_app_number] => 18/374587
[patent_app_country] => US
[patent_app_date] => 2023-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 1081
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374587
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/374587 | Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone | Sep 27, 2023 | Issued |
Array
(
[id] => 19071393
[patent_doc_number] => 20240105819
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-28
[patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/474389
[patent_app_country] => US
[patent_app_date] => 2023-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13853
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18474389
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/474389 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | Sep 25, 2023 | Pending |
Array
(
[id] => 18898612
[patent_doc_number] => 20240014097
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-11
[patent_title] => MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONE
[patent_app_type] => utility
[patent_app_number] => 18/372542
[patent_app_country] => US
[patent_app_date] => 2023-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6181
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18372542
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/372542 | MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONE | Sep 24, 2023 | Pending |