Search

Edward Chin

Examiner (ID: 16584, Phone: (571)270-1827 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2893, 2813, 2821
Total Applications
825
Issued Applications
669
Pending Applications
85
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12779635 [patent_doc_number] => 20180151713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => HEMT HAVING CONDUCTION BARRIER BETWEEN DRAIN FINGERTIP AND SOURCE [patent_app_type] => utility [patent_app_number] => 15/864157 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15864157 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/864157
HEMT having conduction barrier between drain fingertip and source Jan 7, 2018 Issued
Array ( [id] => 12680182 [patent_doc_number] => 20180118560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => Method and Structure for CMOS-MEMS Thin Film Encapsulation [patent_app_type] => utility [patent_app_number] => 15/860357 [patent_app_country] => US [patent_app_date] => 2018-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15860357 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/860357
Method and structure for CMOS-MEMS thin film encapsulation Jan 1, 2018 Issued
Array ( [id] => 13360709 [patent_doc_number] => 20180231894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => SUBSTRATE TREATING METHOD AND APPARATUS USED THEREFOR [patent_app_type] => utility [patent_app_number] => 15/856486 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15856486 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/856486
SUBSTRATE TREATING METHOD AND APPARATUS USED THEREFOR Dec 27, 2017 Abandoned
Array ( [id] => 13360711 [patent_doc_number] => 20180231895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => SUBSTRATE TREATING METHOD [patent_app_type] => utility [patent_app_number] => 15/856500 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15856500 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/856500
Substrate treating method Dec 27, 2017 Issued
Array ( [id] => 13358117 [patent_doc_number] => 20180230598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => SUBSTRATE TREATING METHOD AND APPARATUS USED THEREFOR [patent_app_type] => utility [patent_app_number] => 15/854010 [patent_app_country] => US [patent_app_date] => 2017-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854010 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854010
Substrate treating method and apparatus used therefor Dec 25, 2017 Issued
Array ( [id] => 13358119 [patent_doc_number] => 20180230599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => SUBSTRATE TREATING METHOD [patent_app_type] => utility [patent_app_number] => 15/854011 [patent_app_country] => US [patent_app_date] => 2017-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854011 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854011
Substrate treating method Dec 25, 2017 Issued
Array ( [id] => 12669166 [patent_doc_number] => 20180114888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => LED MODULE [patent_app_type] => utility [patent_app_number] => 15/848993 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848993 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/848993
LED module Dec 19, 2017 Issued
Array ( [id] => 16707795 [patent_doc_number] => 10957739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Resistance variation element, semiconductor device, and manufacturing method [patent_app_type] => utility [patent_app_number] => 16/470617 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6551 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16470617 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/470617
Resistance variation element, semiconductor device, and manufacturing method Dec 17, 2017 Issued
Array ( [id] => 14177671 [patent_doc_number] => 10262856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Selective oxidation of transition metal nitride layers within compound semiconductor device structures [patent_app_type] => utility [patent_app_number] => 15/843041 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 7009 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15843041 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/843041
Selective oxidation of transition metal nitride layers within compound semiconductor device structures Dec 14, 2017 Issued
Array ( [id] => 12872482 [patent_doc_number] => 20180182669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => METHOD OF FILLING A VIA HOLE AND APPARATUS FOR PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/841518 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841518 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/841518
Method of filling a via hole and apparatus for performing the same Dec 13, 2017 Issued
Array ( [id] => 15260105 [patent_doc_number] => 20190378786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => POWER MODULE COMPRISING A HOUSING WHICH IS FORMED IN LEVELS [patent_app_type] => utility [patent_app_number] => 16/470970 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16470970 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/470970
Power module comprising a housing which is formed in levels Dec 10, 2017 Issued
Array ( [id] => 16169326 [patent_doc_number] => 10710872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => MEMS package with roughend interface [patent_app_type] => utility [patent_app_number] => 15/833072 [patent_app_country] => US [patent_app_date] => 2017-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833072 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/833072
MEMS package with roughend interface Dec 5, 2017 Issued
Array ( [id] => 12624111 [patent_doc_number] => 20180099867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => MEMS Device and MEMS Vacuum Microphone [patent_app_type] => utility [patent_app_number] => 15/819767 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819767 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/819767
MEMS device and MEMS vacuum microphone Nov 20, 2017 Issued
Array ( [id] => 14738231 [patent_doc_number] => 10388525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Multi-angled deposition and masking for custom spacer trim and selected spacer removal [patent_app_type] => utility [patent_app_number] => 15/810454 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 10041 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810454 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/810454
Multi-angled deposition and masking for custom spacer trim and selected spacer removal Nov 12, 2017 Issued
Array ( [id] => 12243173 [patent_doc_number] => 20180076035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'MULTI-ANGLED DEPOSITION AND MASKING FOR CUSTOM SPACER TRIM AND SELECTED SPACER REMOVAL' [patent_app_type] => utility [patent_app_number] => 15/810463 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10677 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810463 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/810463
Multi-angled deposition and masking for custom spacer trim and selected spacer removal Nov 12, 2017 Issued
Array ( [id] => 14801237 [patent_doc_number] => 10403629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Six-transistor (6T) SRAM cell structure [patent_app_type] => utility [patent_app_number] => 15/804556 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804556 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/804556
Six-transistor (6T) SRAM cell structure Nov 5, 2017 Issued
Array ( [id] => 13936179 [patent_doc_number] => 20190051605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => HIGH-DENSITY INTERCONNECTING ADHESIVE TAPE [patent_app_type] => utility [patent_app_number] => 15/804364 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804364 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/804364
High-density interconnecting adhesive tape Nov 5, 2017 Issued
Array ( [id] => 16172898 [patent_doc_number] => 10714476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/804307 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 89 [patent_no_of_words] => 11786 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/804307
Semiconductor device Nov 5, 2017 Issued
Array ( [id] => 14285591 [patent_doc_number] => 20190140080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => FABRICATION OF VERTICAL FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED BOTTOM INSULATING SPACERS [patent_app_type] => utility [patent_app_number] => 15/804303 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804303 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/804303
Fabrication of vertical field effect transistors with self-aligned bottom insulating spacers Nov 5, 2017 Issued
Array ( [id] => 16565188 [patent_doc_number] => 10890553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Sensing device, sensing apparatus and sensing system [patent_app_type] => utility [patent_app_number] => 15/804455 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 7462 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804455 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/804455
Sensing device, sensing apparatus and sensing system Nov 5, 2017 Issued
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