
Edward J. Dudek Jr.
Examiner (ID: 15510, Phone: (571)270-1030 , Office: P/2136 )
| Most Active Art Unit | 2136 |
| Art Unit(s) | 2132, 2186, 2136 |
| Total Applications | 1288 |
| Issued Applications | 1108 |
| Pending Applications | 84 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14872253
[patent_doc_number] => 20190286368
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-19
[patent_title] => MANAGEMENT DEVICE AND INFORMATION PROCESSING DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/117806
[patent_app_country] => US
[patent_app_date] => 2018-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13825
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117806
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/117806 | Management device and information processing device | Aug 29, 2018 | Issued |
Array
(
[id] => 15561665
[patent_doc_number] => 20200065244
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-27
[patent_title] => METHODS AND APPARATUS FOR CONTROL OF A JOINTLY SHARED MEMORY-MAPPED REGION
[patent_app_type] => utility
[patent_app_number] => 16/112480
[patent_app_country] => US
[patent_app_date] => 2018-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13587
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16112480
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/112480 | Methods and apparatus for control of a jointly shared memory-mapped region | Aug 23, 2018 | Issued |
Array
(
[id] => 14162067
[patent_doc_number] => 20190108136
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-11
[patent_title] => MEMORY SYSTEM AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/054495
[patent_app_country] => US
[patent_app_date] => 2018-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22567
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054495
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/054495 | Memory system and operation method thereof | Aug 2, 2018 | Issued |
Array
(
[id] => 15638867
[patent_doc_number] => 10592427
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-17
[patent_title] => Logical to physical table fragments
[patent_app_type] => utility
[patent_app_number] => 16/052921
[patent_app_country] => US
[patent_app_date] => 2018-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 8456
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16052921
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/052921 | Logical to physical table fragments | Aug 1, 2018 | Issued |
Array
(
[id] => 14668861
[patent_doc_number] => 10372331
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-06
[patent_title] => Storage system, information processing system and method for controlling nonvolatile memory
[patent_app_type] => utility
[patent_app_number] => 16/037111
[patent_app_country] => US
[patent_app_date] => 2018-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 54
[patent_figures_cnt] => 66
[patent_no_of_words] => 35061
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037111
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/037111 | Storage system, information processing system and method for controlling nonvolatile memory | Jul 16, 2018 | Issued |
Array
(
[id] => 16408863
[patent_doc_number] => 10817416
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-27
[patent_title] => Memory management method and storage controller
[patent_app_type] => utility
[patent_app_number] => 16/036955
[patent_app_country] => US
[patent_app_date] => 2018-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8580
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 380
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16036955
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/036955 | Memory management method and storage controller | Jul 16, 2018 | Issued |
Array
(
[id] => 13540611
[patent_doc_number] => 20180321852
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-08
[patent_title] => CHECK POINTING A SHIFT REGISTER WITH A CIRCULAR BUFFER
[patent_app_type] => utility
[patent_app_number] => 16/036104
[patent_app_country] => US
[patent_app_date] => 2018-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18420
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16036104
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/036104 | Check pointing a shift register with a circular buffer | Jul 15, 2018 | Issued |
Array
(
[id] => 15367491
[patent_doc_number] => 20200019510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-16
[patent_title] => Isolated Performance Domains in a Memory System
[patent_app_type] => utility
[patent_app_number] => 16/035469
[patent_app_country] => US
[patent_app_date] => 2018-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10971
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035469
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/035469 | Isolated performance domains in a memory system | Jul 12, 2018 | Issued |
Array
(
[id] => 15609129
[patent_doc_number] => 10585625
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-10
[patent_title] => Determination of data integrity based on sentinel cells
[patent_app_type] => utility
[patent_app_number] => 16/033430
[patent_app_country] => US
[patent_app_date] => 2018-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4943
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033430
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/033430 | Determination of data integrity based on sentinel cells | Jul 11, 2018 | Issued |
Array
(
[id] => 15854895
[patent_doc_number] => 10642733
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-05-05
[patent_title] => System and method for memory interface load balancing
[patent_app_type] => utility
[patent_app_number] => 16/033314
[patent_app_country] => US
[patent_app_date] => 2018-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5227
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033314
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/033314 | System and method for memory interface load balancing | Jul 11, 2018 | Issued |
Array
(
[id] => 16200793
[patent_doc_number] => 10725956
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-28
[patent_title] => Memory device for a hierarchical memory architecture
[patent_app_type] => utility
[patent_app_number] => 16/025889
[patent_app_country] => US
[patent_app_date] => 2018-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4014
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16025889
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/025889 | Memory device for a hierarchical memory architecture | Jul 1, 2018 | Issued |
Array
(
[id] => 13906429
[patent_doc_number] => 20190042419
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-07
[patent_title] => TECHNOLOGIES FOR DEMOTING CACHE LINES TO SHARED CACHE
[patent_app_type] => utility
[patent_app_number] => 16/024773
[patent_app_country] => US
[patent_app_date] => 2018-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9080
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16024773
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/024773 | Technologies for demoting cache lines to shared cache | Jun 29, 2018 | Issued |
Array
(
[id] => 15924283
[patent_doc_number] => 10659396
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-19
[patent_title] => Joining data within a reconfigurable fabric
[patent_app_type] => utility
[patent_app_number] => 16/021840
[patent_app_country] => US
[patent_app_date] => 2018-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 13535
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16021840
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/021840 | Joining data within a reconfigurable fabric | Jun 27, 2018 | Issued |
Array
(
[id] => 15427371
[patent_doc_number] => 10546620
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-28
[patent_title] => Data strobe calibration
[patent_app_type] => utility
[patent_app_number] => 16/022351
[patent_app_country] => US
[patent_app_date] => 2018-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 14759
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022351
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/022351 | Data strobe calibration | Jun 27, 2018 | Issued |
Array
(
[id] => 13432391
[patent_doc_number] => 20180267738
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-20
[patent_title] => APPARATUSES AND METHODS FOR DATA MOVEMENT
[patent_app_type] => utility
[patent_app_number] => 15/978750
[patent_app_country] => US
[patent_app_date] => 2018-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21349
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15978750
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/978750 | Apparatuses and methods for data movement | May 13, 2018 | Issued |
Array
(
[id] => 13347325
[patent_doc_number] => 20180225202
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-09
[patent_title] => ADAPTIVE STORAGE MANAGEMENT FOR OPTIMIZING MULTI-TIER DATA STORAGE SYSTEM
[patent_app_type] => utility
[patent_app_number] => 15/943883
[patent_app_country] => US
[patent_app_date] => 2018-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7920
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943883
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/943883 | Adaptive storage management for optimizing multi-tier data storage system | Apr 2, 2018 | Issued |
Array
(
[id] => 14076875
[patent_doc_number] => 20190087325
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-21
[patent_title] => MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 15/916385
[patent_app_country] => US
[patent_app_date] => 2018-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11291
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916385
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/916385 | Memory system | Mar 8, 2018 | Issued |
Array
(
[id] => 15788715
[patent_doc_number] => 10628081
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-21
[patent_title] => Managing internal command queues in solid state storage drives
[patent_app_type] => utility
[patent_app_number] => 15/917119
[patent_app_country] => US
[patent_app_date] => 2018-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9588
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15917119
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/917119 | Managing internal command queues in solid state storage drives | Mar 8, 2018 | Issued |
Array
(
[id] => 15486037
[patent_doc_number] => 10558367
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-11
[patent_title] => Adaptive transaction layer packet for latency balancing
[patent_app_type] => utility
[patent_app_number] => 15/916082
[patent_app_country] => US
[patent_app_date] => 2018-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4935
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916082
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/916082 | Adaptive transaction layer packet for latency balancing | Mar 7, 2018 | Issued |
Array
(
[id] => 15672435
[patent_doc_number] => 10600455
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-24
[patent_title] => Memory controllers, systems, and methods supporting multiple request modes
[patent_app_type] => utility
[patent_app_number] => 15/916193
[patent_app_country] => US
[patent_app_date] => 2018-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 7
[patent_no_of_words] => 20265
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916193
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/916193 | Memory controllers, systems, and methods supporting multiple request modes | Mar 7, 2018 | Issued |