
Edward Michael Wacyra
Examiner (ID: 19106)
| Most Active Art Unit | 3102 |
| Art Unit(s) | 3108, 3102, 3101, 2899 |
| Total Applications | 666 |
| Issued Applications | 593 |
| Pending Applications | 0 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15609467
[patent_doc_number] => 10585795
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-10
[patent_title] => Data relocation in memory having two portions of data
[patent_app_type] => utility
[patent_app_number] => 15/994477
[patent_app_country] => US
[patent_app_date] => 2018-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 9336
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994477
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/994477 | Data relocation in memory having two portions of data | May 30, 2018 | Issued |
Array
(
[id] => 16745215
[patent_doc_number] => 10970205
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-06
[patent_title] => Logical-to-physical data structures for tracking logical block addresses indicative of a collision
[patent_app_type] => utility
[patent_app_number] => 15/994669
[patent_app_country] => US
[patent_app_date] => 2018-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 9126
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994669
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/994669 | Logical-to-physical data structures for tracking logical block addresses indicative of a collision | May 30, 2018 | Issued |
Array
(
[id] => 13569169
[patent_doc_number] => 20180336132
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-22
[patent_title] => INFORMATION PROCESSING DEVICE, PROCESSOR, AND TRANSMISSION INFORMATION STORAGE METHOD
[patent_app_type] => utility
[patent_app_number] => 15/983237
[patent_app_country] => US
[patent_app_date] => 2018-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13535
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15983237
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/983237 | INFORMATION PROCESSING DEVICE, PROCESSOR, AND TRANSMISSION INFORMATION STORAGE METHOD | May 17, 2018 | Abandoned |
Array
(
[id] => 15151647
[patent_doc_number] => 20190354301
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-21
[patent_title] => SELECTION COMPONENT THAT IS CONFIGURED BASED ON AN ARCHITECTURE ASSOCIATED WITH MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 15/982978
[patent_app_country] => US
[patent_app_date] => 2018-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6917
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982978
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/982978 | Selection component that is configured based on an architecture associated with memory devices | May 16, 2018 | Issued |
Array
(
[id] => 15027797
[patent_doc_number] => 20190324903
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-24
[patent_title] => STORAGE CACHE MANAGEMENT
[patent_app_type] => utility
[patent_app_number] => 15/982805
[patent_app_country] => US
[patent_app_date] => 2018-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17945
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982805
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/982805 | Priority addresses for storage cache management | May 16, 2018 | Issued |
Array
(
[id] => 14719539
[patent_doc_number] => 20190250833
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-15
[patent_title] => Management Method of Metadata and Memory Device Using the Same
[patent_app_type] => utility
[patent_app_number] => 15/976839
[patent_app_country] => US
[patent_app_date] => 2018-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3252
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976839
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/976839 | Management method of metadata for preventing data loss and memory device using the same | May 9, 2018 | Issued |
Array
(
[id] => 15609111
[patent_doc_number] => 10585615
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-03-10
[patent_title] => Virtual flash system
[patent_app_type] => utility
[patent_app_number] => 15/976056
[patent_app_country] => US
[patent_app_date] => 2018-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5781
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976056
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/976056 | Virtual flash system | May 9, 2018 | Issued |
Array
(
[id] => 15854461
[patent_doc_number] => 10642513
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-05
[patent_title] => Partially de-centralized latch management architectures for storage devices
[patent_app_type] => utility
[patent_app_number] => 15/899142
[patent_app_country] => US
[patent_app_date] => 2018-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 29
[patent_no_of_words] => 15230
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15899142
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/899142 | Partially de-centralized latch management architectures for storage devices | Feb 18, 2018 | Issued |
Array
(
[id] => 15789143
[patent_doc_number] => 10628296
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-04-21
[patent_title] => Data composite for efficient memory transfer in a behavorial recognition system
[patent_app_type] => utility
[patent_app_number] => 15/881182
[patent_app_country] => US
[patent_app_date] => 2018-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 8537
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881182
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/881182 | Data composite for efficient memory transfer in a behavorial recognition system | Jan 25, 2018 | Issued |
Array
(
[id] => 15472403
[patent_doc_number] => 10552075
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-04
[patent_title] => Disk-image deduplication with hash subset in memory
[patent_app_type] => utility
[patent_app_number] => 15/877566
[patent_app_country] => US
[patent_app_date] => 2018-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4916
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15877566
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/877566 | Disk-image deduplication with hash subset in memory | Jan 22, 2018 | Issued |
Array
(
[id] => 15373131
[patent_doc_number] => 10528283
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-07
[patent_title] => System and method to provide persistent storage class memory using NVDIMM-N with an NVDIMM-P footprint
[patent_app_type] => utility
[patent_app_number] => 15/877639
[patent_app_country] => US
[patent_app_date] => 2018-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5434
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15877639
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/877639 | System and method to provide persistent storage class memory using NVDIMM-N with an NVDIMM-P footprint | Jan 22, 2018 | Issued |
Array
(
[id] => 14628681
[patent_doc_number] => 20190227708
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-25
[patent_title] => Apparatus and Methods for Fast and Secure Storage of Data
[patent_app_type] => utility
[patent_app_number] => 15/877567
[patent_app_country] => US
[patent_app_date] => 2018-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2262
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15877567
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/877567 | Apparatus and methods for fast and secure storage of data | Jan 22, 2018 | Issued |
Array
(
[id] => 14629041
[patent_doc_number] => 20190227888
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-25
[patent_title] => HANDLING NODE FAILURE IN MULTI-NODE DATA STORAGE SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 15/877405
[patent_app_country] => US
[patent_app_date] => 2018-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11894
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 303
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15877405
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/877405 | Handling node failure in multi-node data storage systems | Jan 22, 2018 | Issued |
Array
(
[id] => 14630917
[patent_doc_number] => 20190228827
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-25
[patent_title] => Dynamic Management of a NAND Flash Memory
[patent_app_type] => utility
[patent_app_number] => 15/877589
[patent_app_country] => US
[patent_app_date] => 2018-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1378
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15877589
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/877589 | Dynamic Management of a NAND Flash Memory | Jan 22, 2018 | Abandoned |
Array
(
[id] => 14629115
[patent_doc_number] => 20190227925
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-25
[patent_title] => Garbage Collection Method for a Data Storage Apparatus
[patent_app_type] => utility
[patent_app_number] => 15/877547
[patent_app_country] => US
[patent_app_date] => 2018-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3199
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15877547
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/877547 | Garbage collection method for a data storage apparatus by finding and cleaning a victim block | Jan 22, 2018 | Issued |
Array
(
[id] => 13320341
[patent_doc_number] => 20180211708
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-26
[patent_title] => MEMORY SYSTEM AND CONTROL METHOD
[patent_app_type] => utility
[patent_app_number] => 15/876923
[patent_app_country] => US
[patent_app_date] => 2018-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19083
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876923
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/876923 | Memory system that selectively writes in single-level cell mode or multi-level cell mode to reduce program/erase cycles | Jan 21, 2018 | Issued |
Array
(
[id] => 13449173
[patent_doc_number] => 20180276129
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-27
[patent_title] => PRE-FETCHING IN A MEMORY SYSTEM CONFIGURED WITH SYNTHESIZED LOGICAL BLOCKS
[patent_app_type] => utility
[patent_app_number] => 15/876792
[patent_app_country] => US
[patent_app_date] => 2018-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7540
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 21
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876792
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/876792 | PRE-FETCHING IN A MEMORY SYSTEM CONFIGURED WITH SYNTHESIZED LOGICAL BLOCKS | Jan 21, 2018 | Abandoned |
Array
(
[id] => 14887067
[patent_doc_number] => 10423576
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-24
[patent_title] => Optimized caching based on historical production patterns for catalogs
[patent_app_type] => utility
[patent_app_number] => 15/839005
[patent_app_country] => US
[patent_app_date] => 2017-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3309
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839005
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/839005 | Optimized caching based on historical production patterns for catalogs | Dec 11, 2017 | Issued |
Array
(
[id] => 14856807
[patent_doc_number] => 10417131
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-17
[patent_title] => Transactional memory operation success rate
[patent_app_type] => utility
[patent_app_number] => 15/813328
[patent_app_country] => US
[patent_app_date] => 2017-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6638
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813328
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/813328 | Transactional memory operation success rate | Nov 14, 2017 | Issued |
Array
(
[id] => 12161010
[patent_doc_number] => 20180032276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-01
[patent_title] => 'DATA STORAGE IN A MULTI-LEVEL MEMORY DEVICE USING ONE-PASS PROGRAMMING'
[patent_app_type] => utility
[patent_app_number] => 15/728518
[patent_app_country] => US
[patent_app_date] => 2017-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7343
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728518
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/728518 | One-pass programming in a multi-level nonvolatile memory device with improved write amplification | Oct 9, 2017 | Issued |