Search

Edward Michael Wacyra

Examiner (ID: 19106)

Most Active Art Unit
3102
Art Unit(s)
3108, 3102, 3101, 2899
Total Applications
666
Issued Applications
593
Pending Applications
0
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17613683 [patent_doc_number] => 20220155963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => FILE READING METHOD, NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM, AND COMMUNICATION DEVICE [patent_app_type] => utility [patent_app_number] => 17/212172 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212172
File reading method, non-transitory computer readable storage medium, and communication device for reading file from non-volatile memory Mar 24, 2021 Issued
Array ( [id] => 17017148 [patent_doc_number] => 11086789 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-10 [patent_title] => Flash memory drive with erasable segments based upon hierarchical addressing [patent_app_type] => utility [patent_app_number] => 17/213015 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 14460 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213015 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213015
Flash memory drive with erasable segments based upon hierarchical addressing Mar 24, 2021 Issued
Array ( [id] => 17809509 [patent_doc_number] => 20220261344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => GARBAGE COLLECTION OPERATION MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/206149 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17206149 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/206149
Garbage collection operation management based on overall valid page percentage of source block and candidate source block Mar 18, 2021 Issued
Array ( [id] => 18750001 [patent_doc_number] => 11809312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Garbage collection operation management based on overall spare area [patent_app_type] => utility [patent_app_number] => 17/206137 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8870 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17206137 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/206137
Garbage collection operation management based on overall spare area Mar 18, 2021 Issued
Array ( [id] => 17098929 [patent_doc_number] => 20210286720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => MANAGING SNAPSHOTS AND CLONES IN A SCALE OUT STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 17/198556 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198556
MANAGING SNAPSHOTS AND CLONES IN A SCALE OUT STORAGE SYSTEM Mar 10, 2021 Abandoned
Array ( [id] => 16918763 [patent_doc_number] => 20210191855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => LOGICAL-TO-PHYSICAL DATA STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/197660 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197660 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/197660
Logical-to-physical data structures Mar 9, 2021 Issued
Array ( [id] => 17245446 [patent_doc_number] => 20210365189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => PERFORMANCE ANALYSIS APPARATUS AND PERFORMANCE ANALYSIS METHOD [patent_app_type] => utility [patent_app_number] => 17/194538 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194538 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/194538
Performance analysis apparatus and performance analysis method Mar 7, 2021 Issued
Array ( [id] => 17839484 [patent_doc_number] => 20220276789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => EFFECTIVE STORAGE ALLOCATION FOR SEQUENTIALLY-WRITTEN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/187497 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187497 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187497
Effective storage allocation for sequentially-written memory devices Feb 25, 2021 Issued
Array ( [id] => 17083999 [patent_doc_number] => 20210279005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => MEMORY CIRCUIT, INFORMATION PROCESSING CIRCUIT, AND INFORMATION PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/184218 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184218 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184218
Destructive read type memory circuit and information processing circuit and apparatus utilizing destructive read type memory circuit Feb 23, 2021 Issued
Array ( [id] => 17970125 [patent_doc_number] => 11487659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Data storage system capable of performing interleaving scatter transmissions or interleaving gather transmissions [patent_app_type] => utility [patent_app_number] => 17/183314 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3843 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17183314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/183314
Data storage system capable of performing interleaving scatter transmissions or interleaving gather transmissions Feb 22, 2021 Issued
Array ( [id] => 17809507 [patent_doc_number] => 20220261342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => GARBAGE COLLECTION OPERATION MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/179342 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179342 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179342
Garbage collection operation management with early garbage collection starting point Feb 17, 2021 Issued
Array ( [id] => 17581242 [patent_doc_number] => 20220138097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => TRANSACTIONAL ALLOCATION AND DEALLOCATION OF BLOCKS IN A BLOCK STORE [patent_app_type] => utility [patent_app_number] => 17/161323 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161323
Transactional allocation and deallocation of blocks in a block store Jan 27, 2021 Issued
Array ( [id] => 18015211 [patent_doc_number] => 11507509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Memory system, memory controller and method for operating memory system for determining whether to perform direct write based on reference write size [patent_app_type] => utility [patent_app_number] => 17/154980 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154980 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/154980
Memory system, memory controller and method for operating memory system for determining whether to perform direct write based on reference write size Jan 20, 2021 Issued
Array ( [id] => 17970120 [patent_doc_number] => 11487654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Method for controlling write buffer based on states of sectors of write buffer and associated all flash array server [patent_app_type] => utility [patent_app_number] => 17/151645 [patent_app_country] => US [patent_app_date] => 2021-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6938 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17151645 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/151645
Method for controlling write buffer based on states of sectors of write buffer and associated all flash array server Jan 17, 2021 Issued
Array ( [id] => 16826240 [patent_doc_number] => 20210141533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => MEMORY ELEMENT PROFILING AND OPERATIONAL ADJUSTMENTS [patent_app_type] => utility [patent_app_number] => 17/151070 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17151070 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/151070
Memory element profiling and operational adjustments Jan 14, 2021 Issued
Array ( [id] => 17977457 [patent_doc_number] => 11494317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-08 [patent_title] => Memory validation [patent_app_type] => utility [patent_app_number] => 17/137264 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7239 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137264
Memory validation Dec 28, 2020 Issued
Array ( [id] => 17729411 [patent_doc_number] => 11385798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-12 [patent_title] => Method and system for application aware, management of write operations on non-volatile storage [patent_app_type] => utility [patent_app_number] => 17/134577 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11614 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134577 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134577
Method and system for application aware, management of write operations on non-volatile storage Dec 27, 2020 Issued
Array ( [id] => 17636691 [patent_doc_number] => 11347415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Selection component that is configured based on an architecture associated with memory devices [patent_app_type] => utility [patent_app_number] => 17/135476 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6942 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135476 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135476
Selection component that is configured based on an architecture associated with memory devices Dec 27, 2020 Issued
Array ( [id] => 17955213 [patent_doc_number] => 11481318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Method and apparatus, and storage system for translating I/O requests before sending [patent_app_type] => utility [patent_app_number] => 17/135560 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 10838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135560 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135560
Method and apparatus, and storage system for translating I/O requests before sending Dec 27, 2020 Issued
Array ( [id] => 17401655 [patent_doc_number] => 20220043745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => DYNAMIC CONFIGURING OF RELIABILITY AND DENSITY OF NON-VOLATILE MEMORIES [patent_app_type] => utility [patent_app_number] => 17/125833 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125833
Dynamic configuring of reliability and density of non-volatile memories Dec 16, 2020 Issued
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