Search

Edward Thomas Tolan

Examiner (ID: 3664, Phone: (571)272-4525 , Office: P/3725 )

Most Active Art Unit
3725
Art Unit(s)
3201, 3725
Total Applications
2859
Issued Applications
2278
Pending Applications
141
Abandoned Applications
440

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10364467 [patent_doc_number] => 20150249469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-03 [patent_title] => 'TRANSMISSION APPARATUS AND METHOD, AND RECEPTION APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/709175 [patent_app_country] => US [patent_app_date] => 2015-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 49060 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14709175 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/709175
TRANSMISSION APPARATUS AND METHOD, AND RECEPTION APPARATUS AND METHOD May 10, 2015 Abandoned
Array ( [id] => 10818377 [patent_doc_number] => 20160164540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'DATA PROCESSING DEVICE AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 14/903993 [patent_app_country] => US [patent_app_date] => 2015-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 221 [patent_figures_cnt] => 221 [patent_no_of_words] => 69147 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14903993 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/903993
DATA PROCESSING DEVICE AND DATA PROCESSING METHOD May 7, 2015 Abandoned
Array ( [id] => 10609203 [patent_doc_number] => 09329230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Enable and select inputs operate combinational logic parallel scan paths' [patent_app_type] => utility [patent_app_number] => 14/707794 [patent_app_country] => US [patent_app_date] => 2015-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 7865 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14707794 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/707794
Enable and select inputs operate combinational logic parallel scan paths May 7, 2015 Issued
Array ( [id] => 11752316 [patent_doc_number] => 09710328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Semiconductor memory device and operating method thereof' [patent_app_type] => utility [patent_app_number] => 14/705671 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 14043 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705671 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/705671
Semiconductor memory device and operating method thereof May 5, 2015 Issued
Array ( [id] => 11910054 [patent_doc_number] => 09778863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'System and method for folding partial blocks into multi-level cell memory blocks' [patent_app_type] => utility [patent_app_number] => 14/701158 [patent_app_country] => US [patent_app_date] => 2015-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8222 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14701158 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/701158
System and method for folding partial blocks into multi-level cell memory blocks Apr 29, 2015 Issued
Array ( [id] => 10309222 [patent_doc_number] => 20150194224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS' [patent_app_type] => utility [patent_app_number] => 14/664547 [patent_app_country] => US [patent_app_date] => 2015-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4701 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14664547 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/664547
Memory devices and methods for managing error regions Mar 19, 2015 Issued
Array ( [id] => 11931600 [patent_doc_number] => 09798599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Apparatus for monitoring operating conditions of a logic circuit to determine failure of one or more latches' [patent_app_type] => utility [patent_app_number] => 14/631128 [patent_app_country] => US [patent_app_date] => 2015-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10865 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14631128 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/631128
Apparatus for monitoring operating conditions of a logic circuit to determine failure of one or more latches Feb 24, 2015 Issued
Array ( [id] => 10188739 [patent_doc_number] => 09218158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'N-valued shift registers with inverter reduced feedback logic functions' [patent_app_type] => utility [patent_app_number] => 14/622860 [patent_app_country] => US [patent_app_date] => 2015-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 54 [patent_no_of_words] => 20141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14622860 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/622860
N-valued shift registers with inverter reduced feedback logic functions Feb 13, 2015 Issued
Array ( [id] => 10156870 [patent_doc_number] => 09188641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'IC tap/scan selecting between TDI/SI and a test pattern source' [patent_app_type] => utility [patent_app_number] => 14/620778 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 67 [patent_no_of_words] => 20017 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620778 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/620778
IC tap/scan selecting between TDI/SI and a test pattern source Feb 11, 2015 Issued
Array ( [id] => 11272608 [patent_doc_number] => 20160335155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'Method and Device for Storing Data, Method and Device for Decoding Stored Data, and Computer Program Corresponding Thereto' [patent_app_type] => utility [patent_app_number] => 15/111710 [patent_app_country] => US [patent_app_date] => 2015-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11385 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15111710 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/111710
Method and Device for Storing Data, Method and Device for Decoding Stored Data, and Computer Program Corresponding Thereto Jan 12, 2015 Abandoned
Array ( [id] => 11226706 [patent_doc_number] => 09454429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Protection against word line failure in memory devices' [patent_app_type] => utility [patent_app_number] => 14/595578 [patent_app_country] => US [patent_app_date] => 2015-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14595578 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/595578
Protection against word line failure in memory devices Jan 12, 2015 Issued
Array ( [id] => 11344642 [patent_doc_number] => 09529046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Partitioned scan chain diagnostics using multiple bypass structures and injection points' [patent_app_type] => utility [patent_app_number] => 14/573975 [patent_app_country] => US [patent_app_date] => 2014-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5276 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14573975 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/573975
Partitioned scan chain diagnostics using multiple bypass structures and injection points Dec 16, 2014 Issued
Array ( [id] => 11410083 [patent_doc_number] => 09557383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Partitioned scan chain diagnostics using multiple bypass structures and injection points' [patent_app_type] => utility [patent_app_number] => 14/568440 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5231 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14568440 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/568440
Partitioned scan chain diagnostics using multiple bypass structures and injection points Dec 11, 2014 Issued
Array ( [id] => 12060763 [patent_doc_number] => 20170337107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'DATA STORAGE SYSTEM AND DATA STORAGE METHOD' [patent_app_type] => utility [patent_app_number] => 15/533924 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8148 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15533924 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/533924
Data storage system and data storage method Dec 8, 2014 Issued
Array ( [id] => 9919294 [patent_doc_number] => 20150074499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'METHOD OF IDENTIFYING A CORRECT DECODING CODEWORD' [patent_app_type] => utility [patent_app_number] => 14/538654 [patent_app_country] => US [patent_app_date] => 2014-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4625 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14538654 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/538654
METHOD OF IDENTIFYING A CORRECT DECODING CODEWORD Nov 10, 2014 Abandoned
Array ( [id] => 11278768 [patent_doc_number] => 09495247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Time multiplexed redundant array of independent tapes' [patent_app_type] => utility [patent_app_number] => 14/524133 [patent_app_country] => US [patent_app_date] => 2014-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 7279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14524133 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/524133
Time multiplexed redundant array of independent tapes Oct 26, 2014 Issued
Array ( [id] => 14123277 [patent_doc_number] => 10248497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Error detection and correction utilizing locally stored parity information [patent_app_type] => utility [patent_app_number] => 14/521183 [patent_app_country] => US [patent_app_date] => 2014-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5292 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14521183 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/521183
Error detection and correction utilizing locally stored parity information Oct 21, 2014 Issued
Array ( [id] => 11645988 [patent_doc_number] => 09667389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'Device and method for processing HARQ data selectively using internal and external memories' [patent_app_type] => utility [patent_app_number] => 14/518420 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5355 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518420 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/518420
Device and method for processing HARQ data selectively using internal and external memories Oct 19, 2014 Issued
Array ( [id] => 10228350 [patent_doc_number] => 20150113344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'TESTING METHOD, TESTING APPARATUS AND CIRCUIT FOR USE WITH SCAN CHAINS' [patent_app_type] => utility [patent_app_number] => 14/517673 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6178 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517673 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/517673
TESTING METHOD, TESTING APPARATUS AND CIRCUIT FOR USE WITH SCAN CHAINS Oct 16, 2014 Abandoned
Array ( [id] => 10763361 [patent_doc_number] => 20160109516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'Portable and Modular Logic Design Testing Module' [patent_app_type] => utility [patent_app_number] => 14/517362 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517362 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/517362
Portable and Modular Logic Design Testing Module Oct 16, 2014 Abandoned
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