Search

Edward Thomas Tolan

Examiner (ID: 3664, Phone: (571)272-4525 , Office: P/3725 )

Most Active Art Unit
3725
Art Unit(s)
3201, 3725
Total Applications
2859
Issued Applications
2278
Pending Applications
141
Abandoned Applications
440

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10765880 [patent_doc_number] => 20160112036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'FLIP-FLOP CELL WITH CONFIGURABLE DELAY' [patent_app_type] => utility [patent_app_number] => 14/516680 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4122 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14516680 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/516680
Flip-flop cell with configurable delay Oct 16, 2014 Issued
Array ( [id] => 10763364 [patent_doc_number] => 20160109519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'SYSTEM AND METHOD FOR ELIMINATING INDETERMINISM IN INTEGRATED CIRCUIT TESTING' [patent_app_type] => utility [patent_app_number] => 14/516557 [patent_app_country] => US [patent_app_date] => 2014-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3710 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14516557 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/516557
SYSTEM AND METHOD FOR ELIMINATING INDETERMINISM IN INTEGRATED CIRCUIT TESTING Oct 15, 2014 Abandoned
Array ( [id] => 11802152 [patent_doc_number] => 09543043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Method for testing array fuse of semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 14/514477 [patent_app_country] => US [patent_app_date] => 2014-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2459 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14514477 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/514477
Method for testing array fuse of semiconductor apparatus Oct 14, 2014 Issued
Array ( [id] => 13972911 [patent_doc_number] => 10215803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-26 [patent_title] => Method and apparatus for concurrent inter-test response compaction and diagnosis [patent_app_type] => utility [patent_app_number] => 14/515249 [patent_app_country] => US [patent_app_date] => 2014-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 96 [patent_no_of_words] => 17002 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14515249 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/515249
Method and apparatus for concurrent inter-test response compaction and diagnosis Oct 14, 2014 Issued
Array ( [id] => 11818666 [patent_doc_number] => 09722634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Multiple component codes based generalized low-density parity-check codes for high-speed optical transport' [patent_app_type] => utility [patent_app_number] => 14/513975 [patent_app_country] => US [patent_app_date] => 2014-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5557 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14513975 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/513975
Multiple component codes based generalized low-density parity-check codes for high-speed optical transport Oct 13, 2014 Issued
Array ( [id] => 10401518 [patent_doc_number] => 20150286527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'SOLID STATE DRIVE AND ASSOCIATED ERROR CHECK AND CORRECTION METHOD' [patent_app_type] => utility [patent_app_number] => 14/509563 [patent_app_country] => US [patent_app_date] => 2014-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3863 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14509563 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/509563
Solid state drive and associated error check and correction method Oct 7, 2014 Issued
Array ( [id] => 10228357 [patent_doc_number] => 20150113350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'SELECTIVE TEST PATTERN PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/502182 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1797 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14502182 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/502182
Selective test pattern processor Sep 29, 2014 Issued
Array ( [id] => 10688208 [patent_doc_number] => 20160034353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'Storage Module and Method for Improved Error Correction by Detection of Grown Bad Bit Lines' [patent_app_type] => utility [patent_app_number] => 14/502738 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14502738 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/502738
Storage module and method for improved error correction by detection of grown bad bit lines Sep 29, 2014 Issued
Array ( [id] => 10569230 [patent_doc_number] => 09292399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-22 [patent_title] => 'Design-Based weighting for logic built-in self-test' [patent_app_type] => utility [patent_app_number] => 14/501122 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7633 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501122 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501122
Design-Based weighting for logic built-in self-test Sep 29, 2014 Issued
Array ( [id] => 10746155 [patent_doc_number] => 20160092306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'PLATFORM ERROR CORRECTION' [patent_app_type] => utility [patent_app_number] => 14/498616 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7586 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498616 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/498616
Platform error correction Sep 25, 2014 Issued
Array ( [id] => 10703811 [patent_doc_number] => 20160049958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/496627 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6937 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14496627 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/496627
Low density parity check encoder having length of 64800 and code rate of 3/15, and low density parity check encoding method using the same Sep 24, 2014 Issued
Array ( [id] => 10739474 [patent_doc_number] => 20160085625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'SELF-ACCUMULATING EXCLUSIVE OR PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/491544 [patent_app_country] => US [patent_app_date] => 2014-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5754 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14491544 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/491544
Self-accumulating exclusive OR program Sep 18, 2014 Issued
Array ( [id] => 10977072 [patent_doc_number] => 20140380107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITY' [patent_app_type] => utility [patent_app_number] => 14/484736 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9133 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14484736 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/484736
Testing electronic memories based on fault and test algorithm periodicity Sep 11, 2014 Issued
Array ( [id] => 10321598 [patent_doc_number] => 20150206602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'CHIP, OPERATION METHOD, AND MANUFACTURING METHOD OF ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/475584 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475584 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/475584
CHIP, OPERATION METHOD, AND MANUFACTURING METHOD OF ELECTRONIC APPARATUS Sep 2, 2014 Abandoned
Array ( [id] => 10551973 [patent_doc_number] => 09276614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Buffer management in a turbo equalization system' [patent_app_type] => utility [patent_app_number] => 14/464582 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5092 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464582 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464582
Buffer management in a turbo equalization system Aug 19, 2014 Issued
Array ( [id] => 10228349 [patent_doc_number] => 20150113342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'NONVOLATILE MEMORY DEVICE INCLUDING DUMMY WORDLINE, MEMORY SYSTEM, AND METHOD OF OPERATING MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/463130 [patent_app_country] => US [patent_app_date] => 2014-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10291 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14463130 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/463130
Nonvolatile memory device including dummy wordline, memory system, and method of operating memory system Aug 18, 2014 Issued
Array ( [id] => 10956366 [patent_doc_number] => 20140359388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'CORE CIRCUIT TEST ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/460855 [patent_app_country] => US [patent_app_date] => 2014-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7825 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14460855 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/460855
Wired-or fail flag in serial stimulus, expected/mask data test circuitry Aug 14, 2014 Issued
Array ( [id] => 10575782 [patent_doc_number] => 09298422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Noise generator, integrated circuit including the same, and operation method thereof' [patent_app_type] => utility [patent_app_number] => 14/446029 [patent_app_country] => US [patent_app_date] => 2014-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14446029 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/446029
Noise generator, integrated circuit including the same, and operation method thereof Jul 28, 2014 Issued
Array ( [id] => 10561756 [patent_doc_number] => 09285424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Method and system for logic built-in self-test' [patent_app_type] => utility [patent_app_number] => 14/340577 [patent_app_country] => US [patent_app_date] => 2014-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3080 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14340577 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/340577
Method and system for logic built-in self-test Jul 24, 2014 Issued
Array ( [id] => 10660318 [patent_doc_number] => 20160006462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'NON-VOLATILE MEMORY CONTROLLER WITH ERROR CORRECTION (ECC) TUNING VIA ERROR STATISTICS COLLECTION' [patent_app_type] => utility [patent_app_number] => 14/325244 [patent_app_country] => US [patent_app_date] => 2014-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7546 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14325244 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/325244
Non-volatile memory controller with error correction (ECC) tuning via error statistics collection Jul 6, 2014 Issued
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