Search

Edward Thomas Tolan

Examiner (ID: 3664, Phone: (571)272-4525 , Office: P/3725 )

Most Active Art Unit
3725
Art Unit(s)
3201, 3725
Total Applications
2859
Issued Applications
2278
Pending Applications
141
Abandoned Applications
440

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16495529 [patent_doc_number] => 10861576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Nonvolatile memory device, operating method thereof and data storage device including the same [patent_app_type] => utility [patent_app_number] => 16/153079 [patent_app_country] => US [patent_app_date] => 2018-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7579 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16153079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/153079
Nonvolatile memory device, operating method thereof and data storage device including the same Oct 4, 2018 Issued
Array ( [id] => 14347427 [patent_doc_number] => 20190155686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => SOFT CHIP-KILL RECOVERY USING CONCATENATED CODES [patent_app_type] => utility [patent_app_number] => 16/151064 [patent_app_country] => US [patent_app_date] => 2018-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16151064 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/151064
Soft chip-kill recovery using concatenated codes Oct 2, 2018 Issued
Array ( [id] => 15685391 [patent_doc_number] => 20200097359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => COMMON HIGH AND LOW RANDOM BIT ERROR CORRECTION LOGIC [patent_app_type] => utility [patent_app_number] => 16/142440 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16142440 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/142440
Common high and low random bit error correction logic Sep 25, 2018 Issued
Array ( [id] => 13845385 [patent_doc_number] => 20190026177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => REPORTING ERRORS TO A DATA STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/141620 [patent_app_country] => US [patent_app_date] => 2018-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16141620 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/141620
Reporting errors to a data storage device Sep 24, 2018 Issued
Array ( [id] => 16403051 [patent_doc_number] => 20200343909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => METHODS AND APPARATUS FOR CRC CONCATENATED POLAR ENCODING [patent_app_type] => utility [patent_app_number] => 16/760758 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16760758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/760758
Methods and apparatus for CRC concatenated polar encoding Sep 20, 2018 Issued
Array ( [id] => 14802535 [patent_doc_number] => 10404281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Low density parity check encoder having length of 64800 and code rate of 3/15, and low density parity check encoding method using the same [patent_app_type] => utility [patent_app_number] => 16/136073 [patent_app_country] => US [patent_app_date] => 2018-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6676 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 810 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16136073 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/136073
Low density parity check encoder having length of 64800 and code rate of 3/15, and low density parity check encoding method using the same Sep 18, 2018 Issued
Array ( [id] => 15231741 [patent_doc_number] => 10503593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Two layer quad bit error correction [patent_app_type] => utility [patent_app_number] => 16/125117 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16125117 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/125117
Two layer quad bit error correction Sep 6, 2018 Issued
Array ( [id] => 16844755 [patent_doc_number] => 11016842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Methods and apparatus to detect and correct errors in destructive read non-volatile memory [patent_app_type] => utility [patent_app_number] => 16/122575 [patent_app_country] => US [patent_app_date] => 2018-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 9902 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16122575 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/122575
Methods and apparatus to detect and correct errors in destructive read non-volatile memory Sep 4, 2018 Issued
Array ( [id] => 14921789 [patent_doc_number] => 10432229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 2/15 and 16-symbol mapping, and bit interleaving method using same [patent_app_type] => utility [patent_app_number] => 16/122667 [patent_app_country] => US [patent_app_date] => 2018-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5700 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16122667 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/122667
Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 2/15 and 16-symbol mapping, and bit interleaving method using same Sep 4, 2018 Issued
Array ( [id] => 16972371 [patent_doc_number] => 11068343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Data storage error protection [patent_app_type] => utility [patent_app_number] => 16/110033 [patent_app_country] => US [patent_app_date] => 2018-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 11004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16110033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/110033
Data storage error protection Aug 22, 2018 Issued
Array ( [id] => 17379888 [patent_doc_number] => 11237904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Tracking data access in a dispersed storage network [patent_app_type] => utility [patent_app_number] => 16/050533 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7943 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050533 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050533
Tracking data access in a dispersed storage network Jul 30, 2018 Issued
Array ( [id] => 14921797 [patent_doc_number] => 10432233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-01 [patent_title] => Error correction processing in a storage device [patent_app_type] => utility [patent_app_number] => 16/028933 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6451 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16028933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/028933
Error correction processing in a storage device Jul 5, 2018 Issued
Array ( [id] => 15201705 [patent_doc_number] => 10498365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Data processing device and data processing method [patent_app_type] => utility [patent_app_number] => 16/007601 [patent_app_country] => US [patent_app_date] => 2018-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 220 [patent_figures_cnt] => 220 [patent_no_of_words] => 67027 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 962 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16007601 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/007601
Data processing device and data processing method Jun 12, 2018 Issued
Array ( [id] => 16036653 [patent_doc_number] => 10680763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Dynamic scheduling for hybrid automatic repeat request transmission time interval bundling in a communication system [patent_app_type] => utility [patent_app_number] => 16/003771 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 18770 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16003771 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/003771
Dynamic scheduling for hybrid automatic repeat request transmission time interval bundling in a communication system Jun 7, 2018 Issued
Array ( [id] => 15822627 [patent_doc_number] => 10636507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Memory-testing methods for testing memory having error-correcting code [patent_app_type] => utility [patent_app_number] => 16/003523 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3823 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16003523 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/003523
Memory-testing methods for testing memory having error-correcting code Jun 7, 2018 Issued
Array ( [id] => 15261331 [patent_doc_number] => 20190379399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => LOG-LIKELIHOOD-RATIO (LLR) GENERATION ALGORITHM FOR LOW-DENSITY-PARITY-CHECK (LDPC) CODES USED IN FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 16/004273 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16004273 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/004273
LOG-LIKELIHOOD-RATIO (LLR) GENERATION ALGORITHM FOR LOW-DENSITY-PARITY-CHECK (LDPC) CODES USED IN FLASH MEMORY Jun 7, 2018 Abandoned
Array ( [id] => 14313999 [patent_doc_number] => 20190146703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => MEMORY DEVICE HAVING GLOBAL LINE GROUPS IN WHICH DATA INPUT AND OUTPUT UNITS ARE DIFFERENT FROM EACH OTHER [patent_app_type] => utility [patent_app_number] => 16/002298 [patent_app_country] => US [patent_app_date] => 2018-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16002298 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/002298
Memory device having global line groups in which data input and output units are different from each other Jun 6, 2018 Issued
Array ( [id] => 13615007 [patent_doc_number] => 20180359054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => Channel-Adaptive Error-Detecting Codes with Guaranteed Residual Error Probability [patent_app_type] => utility [patent_app_number] => 16/001164 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001164 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001164
Channel adaptive error-detecting codes with guaranteed residual error probability Jun 5, 2018 Issued
Array ( [id] => 16294336 [patent_doc_number] => 10771194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Interconnection network for integrated circuit [patent_app_type] => utility [patent_app_number] => 15/989226 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 17770 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989226 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989226
Interconnection network for integrated circuit May 24, 2018 Issued
Array ( [id] => 15202111 [patent_doc_number] => 10498570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Data communication systems with forward error correction [patent_app_type] => utility [patent_app_number] => 15/986085 [patent_app_country] => US [patent_app_date] => 2018-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 10211 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15986085 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/986085
Data communication systems with forward error correction May 21, 2018 Issued
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