![](/images/general/no_picture/200_user.png)
Edward Thomas Tolan
Examiner (ID: 3664, Phone: (571)272-4525 , Office: P/3725 )
Most Active Art Unit | 3725 |
Art Unit(s) | 3201, 3725 |
Total Applications | 2859 |
Issued Applications | 2278 |
Pending Applications | 141 |
Abandoned Applications | 440 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 16065173
[patent_doc_number] => 10691536
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-23
[patent_title] => Method to select flash memory blocks for refresh after read operations
[patent_app_type] => utility
[patent_app_number] => 15/981648
[patent_app_country] => US
[patent_app_date] => 2018-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8272
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981648
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/981648 | Method to select flash memory blocks for refresh after read operations | May 15, 2018 | Issued |
Array
(
[id] => 14190771
[patent_doc_number] => 20190115091
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-18
[patent_title] => BYTE ENABLE MEMORY BUILT-IN SELF-TEST (MBIST) ALGORITHM
[patent_app_type] => utility
[patent_app_number] => 15/964050
[patent_app_country] => US
[patent_app_date] => 2018-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7872
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964050
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/964050 | Byte enable memory built-in self-test (MBIST) algorithm | Apr 25, 2018 | Issued |
Array
(
[id] => 15029951
[patent_doc_number] => 20190325980
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-24
[patent_title] => LEVEL-CROSSING MEMORY TRACE INSPECTION QUERIES
[patent_app_type] => utility
[patent_app_number] => 15/960177
[patent_app_country] => US
[patent_app_date] => 2018-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22576
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960177
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/960177 | Level-crossing memory trace inspection queries | Apr 22, 2018 | Issued |
Array
(
[id] => 16322384
[patent_doc_number] => 10782343
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => Digital tests with radiation induced upsets
[patent_app_type] => utility
[patent_app_number] => 15/954650
[patent_app_country] => US
[patent_app_date] => 2018-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5808
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15954650
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/954650 | Digital tests with radiation induced upsets | Apr 16, 2018 | Issued |
Array
(
[id] => 17327140
[patent_doc_number] => 11218171
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-04
[patent_title] => Shortened LDPC codes with repetition of code bits for low throughput networks
[patent_app_type] => utility
[patent_app_number] => 16/603244
[patent_app_country] => US
[patent_app_date] => 2018-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 23
[patent_no_of_words] => 13738
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603244
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/603244 | Shortened LDPC codes with repetition of code bits for low throughput networks | Apr 11, 2018 | Issued |
Array
(
[id] => 14970407
[patent_doc_number] => 20190312682
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-10
[patent_title] => RETRANSMISSION OF FAILED TRANSPORT BLOCKS FOR 5G OR OTHER NEXT GENERATION NETWORK
[patent_app_type] => utility
[patent_app_number] => 15/947430
[patent_app_country] => US
[patent_app_date] => 2018-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12051
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15947430
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/947430 | Retransmission of failed transport blocks for 5G or other next generation network | Apr 5, 2018 | Issued |
Array
(
[id] => 17366678
[patent_doc_number] => 11233716
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-25
[patent_title] => System for real-time monitoring with backward error correction
[patent_app_type] => utility
[patent_app_number] => 15/938441
[patent_app_country] => US
[patent_app_date] => 2018-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5660
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15938441
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/938441 | System for real-time monitoring with backward error correction | Mar 27, 2018 | Issued |
Array
(
[id] => 16069069
[patent_doc_number] => 10693502
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-23
[patent_title] => Transmission apparatus and method, and reception apparatus and method
[patent_app_type] => utility
[patent_app_number] => 15/928903
[patent_app_country] => US
[patent_app_date] => 2018-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 46
[patent_no_of_words] => 42726
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15928903
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/928903 | Transmission apparatus and method, and reception apparatus and method | Mar 21, 2018 | Issued |
Array
(
[id] => 13740175
[patent_doc_number] => 20180374557
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-27
[patent_title] => MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS
[patent_app_type] => utility
[patent_app_number] => 15/927679
[patent_app_country] => US
[patent_app_date] => 2018-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4617
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15927679
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/927679 | Memory devices and methods for managing error regions | Mar 20, 2018 | Issued |
Array
(
[id] => 14553847
[patent_doc_number] => 10345376
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-07-09
[patent_title] => Binary signal generator
[patent_app_type] => utility
[patent_app_number] => 15/901444
[patent_app_country] => US
[patent_app_date] => 2018-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3349
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15901444
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/901444 | Binary signal generator | Feb 20, 2018 | Issued |
Array
(
[id] => 16496568
[patent_doc_number] => 10862625
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-08
[patent_title] => Polarization weight calculation for punctured polar code
[patent_app_type] => utility
[patent_app_number] => 16/476890
[patent_app_country] => US
[patent_app_date] => 2018-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 16082
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16476890
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/476890 | Polarization weight calculation for punctured polar code | Feb 16, 2018 | Issued |
Array
(
[id] => 16974250
[patent_doc_number] => 11070235
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-20
[patent_title] => Transmission method and reception device
[patent_app_type] => utility
[patent_app_number] => 16/477138
[patent_app_country] => US
[patent_app_date] => 2018-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 201
[patent_figures_cnt] => 214
[patent_no_of_words] => 77836
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 1104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16477138
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/477138 | Transmission method and reception device | Feb 5, 2018 | Issued |
Array
(
[id] => 15261335
[patent_doc_number] => 20190379401
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-12
[patent_title] => TRANSMISSION METHOD AND RECEPTION DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/477084
[patent_app_country] => US
[patent_app_date] => 2018-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 77398
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 1067
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16477084
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/477084 | Transmission method and reception device | Feb 5, 2018 | Issued |
Array
(
[id] => 14589489
[patent_doc_number] => 20190222353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-18
[patent_title] => TWO BIT ERROR CALIBRATION DEVICE FOR 128 BIT TRANSFER AND THE METHOD FOR PERFORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/873908
[patent_app_country] => US
[patent_app_date] => 2018-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3926
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 500
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873908
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/873908 | Two bit error calibration device for 128 bit transfer and the method for performing the same | Jan 17, 2018 | Issued |
Array
(
[id] => 16322390
[patent_doc_number] => 10782349
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => Test interface board having a transmission line to merge signals, test method using the same, and test system including the same
[patent_app_type] => utility
[patent_app_number] => 15/871278
[patent_app_country] => US
[patent_app_date] => 2018-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7684
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871278
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/871278 | Test interface board having a transmission line to merge signals, test method using the same, and test system including the same | Jan 14, 2018 | Issued |
Array
(
[id] => 14574817
[patent_doc_number] => 20190215016
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-11
[patent_title] => CODE RATE SWITCHING MECHANISM FOR FLASH MEMORY
[patent_app_type] => utility
[patent_app_number] => 15/868868
[patent_app_country] => US
[patent_app_date] => 2018-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6713
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868868
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/868868 | Code rate switching mechanism for flash memory | Jan 10, 2018 | Issued |
Array
(
[id] => 14569561
[patent_doc_number] => 20190212387
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-11
[patent_title] => ON-CHIP CLOCK CONTROL MONITORING
[patent_app_type] => utility
[patent_app_number] => 15/864584
[patent_app_country] => US
[patent_app_date] => 2018-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3592
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15864584
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/864584 | On-chip clock control monitoring | Jan 7, 2018 | Issued |
Array
(
[id] => 12646773
[patent_doc_number] => 20180107422
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-19
[patent_title] => OPTIMIZING DATA STORAGE IN A DISPERSED STORAGE NETWORK
[patent_app_type] => utility
[patent_app_number] => 15/841990
[patent_app_country] => US
[patent_app_date] => 2017-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9039
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841990
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/841990 | Optimizing data storage in a dispersed storage network | Dec 13, 2017 | Issued |
Array
(
[id] => 17048727
[patent_doc_number] => 11101925
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-24
[patent_title] => Decomposable forward error correction
[patent_app_type] => utility
[patent_app_number] => 15/842331
[patent_app_country] => US
[patent_app_date] => 2017-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 24
[patent_no_of_words] => 9661
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842331
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/842331 | Decomposable forward error correction | Dec 13, 2017 | Issued |
Array
(
[id] => 14442131
[patent_doc_number] => 20190178938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-13
[patent_title] => Non-Intrusive On-Chip Analog Test/Trim/Calibrate Subsystem
[patent_app_type] => utility
[patent_app_number] => 15/839174
[patent_app_country] => US
[patent_app_date] => 2017-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8833
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839174
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/839174 | Non-intrusive on-chip analog test/trim/calibrate subsystem | Dec 11, 2017 | Issued |