Search

Edward Thomas Tolan

Examiner (ID: 3664, Phone: (571)272-4525 , Office: P/3725 )

Most Active Art Unit
3725
Art Unit(s)
3201, 3725
Total Applications
2859
Issued Applications
2278
Pending Applications
141
Abandoned Applications
440

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12034331 [patent_doc_number] => 20170324427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/656931 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 53422 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15656931 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/656931
Transmitting apparatus and interleaving method thereof Jul 20, 2017 Issued
Array ( [id] => 14267293 [patent_doc_number] => 10283216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Data storage device and data maintenance method thereof [patent_app_type] => utility [patent_app_number] => 15/649394 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5365 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649394
Data storage device and data maintenance method thereof Jul 12, 2017 Issued
Array ( [id] => 13725899 [patent_doc_number] => 20170373905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => APPARATUS AND METHOD FOR SENDING AND RECEIVING BROADCAST SIGNALS [patent_app_type] => utility [patent_app_number] => 15/646938 [patent_app_country] => US [patent_app_date] => 2017-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15646938 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/646938
Apparatus and method for sending and receiving broadcast signals Jul 10, 2017 Issued
Array ( [id] => 16036657 [patent_doc_number] => 10680765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Control information transmission method, and apparatus [patent_app_type] => utility [patent_app_number] => 15/637752 [patent_app_country] => US [patent_app_date] => 2017-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 20934 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15637752 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/637752
Control information transmission method, and apparatus Jun 28, 2017 Issued
Array ( [id] => 14982523 [patent_doc_number] => 10445173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Method and device for programming non-volatile memory [patent_app_type] => utility [patent_app_number] => 15/632460 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6668 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15632460 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/632460
Method and device for programming non-volatile memory Jun 25, 2017 Issued
Array ( [id] => 13512021 [patent_doc_number] => 20180307553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS [patent_app_type] => utility [patent_app_number] => 15/630516 [patent_app_country] => US [patent_app_date] => 2017-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15630516 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/630516
Delay fault testing of pseudo static controls Jun 21, 2017 Issued
Array ( [id] => 13627111 [patent_doc_number] => 20180365107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => Data Recovery and Regeneration Using Parity Code [patent_app_type] => utility [patent_app_number] => 15/626027 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15626027 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/626027
Data recovery and regeneration using parity code Jun 15, 2017 Issued
Array ( [id] => 13668939 [patent_doc_number] => 10164658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 3/15 and 256-symbol mapping, and bit interleaving method using same [patent_app_type] => utility [patent_app_number] => 15/615594 [patent_app_country] => US [patent_app_date] => 2017-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5822 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15615594 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/615594
Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 3/15 and 256-symbol mapping, and bit interleaving method using same Jun 5, 2017 Issued
Array ( [id] => 14956735 [patent_doc_number] => 10439654 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-08 [patent_title] => Systems, methods and computer program products including features of transforming data involving a secure format from which the data is recoverable [patent_app_type] => utility [patent_app_number] => 15/614608 [patent_app_country] => US [patent_app_date] => 2017-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 31 [patent_no_of_words] => 19564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15614608 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/614608
Systems, methods and computer program products including features of transforming data involving a secure format from which the data is recoverable Jun 5, 2017 Issued
Array ( [id] => 13922671 [patent_doc_number] => 10205467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 256-symbol mapping, and bit interleaving method using same [patent_app_type] => utility [patent_app_number] => 15/612972 [patent_app_country] => US [patent_app_date] => 2017-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5670 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15612972 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/612972
Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 256-symbol mapping, and bit interleaving method using same Jun 1, 2017 Issued
Array ( [id] => 13160947 [patent_doc_number] => 10097211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 2/15 and 16-symbol mapping, and bit interleaving method using same [patent_app_type] => utility [patent_app_number] => 15/612801 [patent_app_country] => US [patent_app_date] => 2017-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5617 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15612801 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/612801
Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 2/15 and 16-symbol mapping, and bit interleaving method using same Jun 1, 2017 Issued
Array ( [id] => 14673649 [patent_doc_number] => 10374754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Polar code rate matching method and apparatus, and wireless communications device [patent_app_type] => utility [patent_app_number] => 15/608060 [patent_app_country] => US [patent_app_date] => 2017-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 13964 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15608060 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/608060
Polar code rate matching method and apparatus, and wireless communications device May 29, 2017 Issued
Array ( [id] => 13580005 [patent_doc_number] => 20180341551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => LAYERED ERROR CORRECTION ENCODING FOR LARGE SCALE DISTRIBUTED OBJECT STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 15/605906 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15605906 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/605906
Layered error correction encoding for large scale distributed object storage system May 24, 2017 Issued
Array ( [id] => 15141031 [patent_doc_number] => 10484014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Controller, semiconductor memory system and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/602255 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10270 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15602255 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/602255
Controller, semiconductor memory system and operating method thereof May 22, 2017 Issued
Array ( [id] => 14397351 [patent_doc_number] => 10311964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Memory control circuit and memory test method [patent_app_type] => utility [patent_app_number] => 15/598077 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5141 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15598077 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/598077
Memory control circuit and memory test method May 16, 2017 Issued
Array ( [id] => 15400745 [patent_doc_number] => 10541032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Responding to power loss [patent_app_type] => utility [patent_app_number] => 15/591700 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 11797 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15591700 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/591700
Responding to power loss May 9, 2017 Issued
Array ( [id] => 13281577 [patent_doc_number] => 10152373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Methods of operating memory including receipt of ECC data [patent_app_type] => utility [patent_app_number] => 15/581374 [patent_app_country] => US [patent_app_date] => 2017-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15581374 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/581374
Methods of operating memory including receipt of ECC data Apr 27, 2017 Issued
Array ( [id] => 14877057 [patent_doc_number] => 20190288770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => APPARATUSES AND METHODS FOR USING ARQ PROCESSES IN A RELAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/300657 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16300657 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/300657
Apparatuses and methods for using ARQ processes in a relay device Apr 26, 2017 Issued
Array ( [id] => 11853111 [patent_doc_number] => 20170227604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/499373 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 20093 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499373 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/499373
Control I/O coupling scan test port to test access port Apr 26, 2017 Issued
Array ( [id] => 14521777 [patent_doc_number] => 10338139 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-02 [patent_title] => Method and apparatus for scan chain reordering and optimization in physical implementation of digital integrated circuits with on-chip test compression [patent_app_type] => utility [patent_app_number] => 15/487428 [patent_app_country] => US [patent_app_date] => 2017-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15487428 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/487428
Method and apparatus for scan chain reordering and optimization in physical implementation of digital integrated circuits with on-chip test compression Apr 12, 2017 Issued
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