Search

Edward Thomas Tolan

Examiner (ID: 3664, Phone: (571)272-4525 , Office: P/3725 )

Most Active Art Unit
3725
Art Unit(s)
3201, 3725
Total Applications
2859
Issued Applications
2278
Pending Applications
141
Abandoned Applications
440

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12188523 [patent_doc_number] => 20180047459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'MEMORY APPARATUS HAVING PLURALITY OF INFORMATION STORAGE TABLES MANAGED BY SEPARATE VIRTUAL REGIONS AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/486932 [patent_app_country] => US [patent_app_date] => 2017-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13913 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15486932 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/486932
Memory apparatus having plurality of information storage tables managed by separate virtual regions and control method thereof Apr 12, 2017 Issued
Array ( [id] => 13499317 [patent_doc_number] => 20180301201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => METHODS AND APPARATUS FOR DETECTING DEFECTS IN MEMORY CIRCUITRY [patent_app_type] => utility [patent_app_number] => 15/485543 [patent_app_country] => US [patent_app_date] => 2017-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15485543 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/485543
Methods and apparatus for detecting defects in memory circuitry Apr 11, 2017 Issued
Array ( [id] => 12006273 [patent_doc_number] => 20170310428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'LINE CARD AND LINE CARD CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 15/484494 [patent_app_country] => US [patent_app_date] => 2017-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7919 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15484494 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/484494
LINE CARD AND LINE CARD CONTROL METHOD Apr 10, 2017 Abandoned
Array ( [id] => 14138987 [patent_doc_number] => 20190103883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => JOINT SOURCE AND POLAR CODING [patent_app_type] => utility [patent_app_number] => 16/087256 [patent_app_country] => US [patent_app_date] => 2017-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16087256 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/087256
JOINT SOURCE AND POLAR CODING Mar 27, 2017 Abandoned
Array ( [id] => 13160941 [patent_doc_number] => 10097208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Error locator polynomial decoder method [patent_app_type] => utility [patent_app_number] => 15/456648 [patent_app_country] => US [patent_app_date] => 2017-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 23375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15456648 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/456648
Error locator polynomial decoder method Mar 12, 2017 Issued
Array ( [id] => 11968049 [patent_doc_number] => 20170272202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'DATA CODING METHODS FOR A COMMUNICATION BETWEEN SEMICONDUCTOR CHIPS' [patent_app_type] => utility [patent_app_number] => 15/442968 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15442968 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/442968
Data coding methods for a communication between semiconductor chips Feb 26, 2017 Issued
Array ( [id] => 11696164 [patent_doc_number] => 20170171881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING SCHEDULING ASSIGNMENTS IN A COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/431206 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5606 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431206 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/431206
Method and apparatus for transmitting and receiving scheduling assignments in a communication system Feb 12, 2017 Issued
Array ( [id] => 12062493 [patent_doc_number] => 20170338837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'USE OF ERROR CORRECTING CODE TO CARRY ADDITIONAL DATA BITS' [patent_app_type] => utility [patent_app_number] => 15/412763 [patent_app_country] => US [patent_app_date] => 2017-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 18512 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15412763 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/412763
Use of error correcting code to carry additional data bits Jan 22, 2017 Issued
Array ( [id] => 11719056 [patent_doc_number] => 20170187555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'PULSE AMPLITUDE MODULATION (PAM) DATA COMMUNICATION WITH FORWARD ERROR CORRECTION' [patent_app_type] => utility [patent_app_number] => 15/405020 [patent_app_country] => US [patent_app_date] => 2017-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10767 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15405020 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/405020
Data communication systems with forward error correction Jan 11, 2017 Issued
Array ( [id] => 12797128 [patent_doc_number] => 20180157545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => FUNCTIONAL INTERCONNECT REDUNDANCY IN CACHE COHERENT SYSTEMS [patent_app_type] => utility [patent_app_number] => 15/391727 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391727 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/391727
Functional interconnect redundancy in cache coherent systems Dec 26, 2016 Issued
Array ( [id] => 11556731 [patent_doc_number] => 20170102977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'METHOD AND APPARATUS FOR DETERMINING STATUS ELEMENT TOTAL WITH SEQUENTIALLY COUPLED COUNTING STATUS CIRCUITS' [patent_app_type] => utility [patent_app_number] => 15/389238 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6329 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389238 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389238
Method and apparatus for determining status element total with sequentially coupled counting status circuits Dec 21, 2016 Issued
Array ( [id] => 13230393 [patent_doc_number] => 10128983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Transmitter and receiver devices performing repetition before interleaving and puncturing after interleaving and methods thereof [patent_app_type] => utility [patent_app_number] => 15/377688 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 10777 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377688 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/377688
Transmitter and receiver devices performing repetition before interleaving and puncturing after interleaving and methods thereof Dec 12, 2016 Issued
Array ( [id] => 15062919 [patent_doc_number] => 10461777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Error locator polynomial decoder and method [patent_app_type] => utility [patent_app_number] => 15/373313 [patent_app_country] => US [patent_app_date] => 2016-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 17324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15373313 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/373313
Error locator polynomial decoder and method Dec 7, 2016 Issued
Array ( [id] => 11503770 [patent_doc_number] => 20170077954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'METHODS AND APPARATUSES FOR CONSTRUCTING PUNCTURED POLAR CODE' [patent_app_type] => utility [patent_app_number] => 15/363028 [patent_app_country] => US [patent_app_date] => 2016-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11219 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15363028 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/363028
Methods and apparatuses for constructing punctured polar code Nov 28, 2016 Issued
Array ( [id] => 11500753 [patent_doc_number] => 20170074938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'IMPROVED CORE CIRCUIT TEST ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/359785 [patent_app_country] => US [patent_app_date] => 2016-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7943 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/359785
IC cores, scan paths, compare circuitry, select and enable inputs Nov 22, 2016 Issued
Array ( [id] => 13800575 [patent_doc_number] => 20190013826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => CIRCUIT DEVICE, ELECTRO-OPTICAL DEVICE, ELECTRONIC APPARATUS, MOBILE BODY, AND ERROR DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 16/060063 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16060063 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/060063
Circuit device, electro-optical device, electronic apparatus, mobile body, and error detection method Nov 17, 2016 Issued
Array ( [id] => 11460545 [patent_doc_number] => 20170054451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/346004 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6958 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15346004 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/346004
Low density parity check encoder having length of 64800 and code rate of 3/15, and low density parity check encoding method using the same Nov 7, 2016 Issued
Array ( [id] => 12712771 [patent_doc_number] => 20180129423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => MEMORY OPERATIONS ON DATA [patent_app_type] => utility [patent_app_number] => 15/345783 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345783 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345783
Memory operations on data Nov 7, 2016 Issued
Array ( [id] => 14708591 [patent_doc_number] => 10382065 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-13 [patent_title] => Iterative outer code recovery using data from multiple reads [patent_app_type] => utility [patent_app_number] => 15/345437 [patent_app_country] => US [patent_app_date] => 2016-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345437 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345437
Iterative outer code recovery using data from multiple reads Nov 6, 2016 Issued
Array ( [id] => 12713194 [patent_doc_number] => 20180129564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => METHOD AND DECODER TO ADJUST AN ERROR LOCATOR POLYNOMIAL BASED ON AN ERROR PARITY [patent_app_type] => utility [patent_app_number] => 15/343866 [patent_app_country] => US [patent_app_date] => 2016-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15343866 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/343866
Method and decoder to adjust an error locator polynomial based on an error parity Nov 3, 2016 Issued
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