Search

Edwin Young

Examiner (ID: 7742, Phone: (571)272-4781 , Office: P/3659 )

Most Active Art Unit
3655
Art Unit(s)
3659, 3681, 3655
Total Applications
2039
Issued Applications
1854
Pending Applications
95
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5852814 [patent_doc_number] => 20060236005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Information input/output device of mobile apparatus' [patent_app_type] => utility [patent_app_number] => 11/129611 [patent_app_country] => US [patent_app_date] => 2005-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2512 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20060236005.pdf [firstpage_image] =>[orig_patent_app_number] => 11129611 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/129611
Information input/output device of mobile apparatus May 12, 2005 Abandoned
Array ( [id] => 558912 [patent_doc_number] => 07177972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Peripherals of computer' [patent_app_type] => utility [patent_app_number] => 11/113996 [patent_app_country] => US [patent_app_date] => 2005-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 12287 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/177/07177972.pdf [firstpage_image] =>[orig_patent_app_number] => 11113996 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/113996
Peripherals of computer Apr 25, 2005 Issued
Array ( [id] => 615672 [patent_doc_number] => 07149828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Bus arbitration apparatus and bus arbitration method' [patent_app_type] => utility [patent_app_number] => 11/113970 [patent_app_country] => US [patent_app_date] => 2005-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 37 [patent_no_of_words] => 16706 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149828.pdf [firstpage_image] =>[orig_patent_app_number] => 11113970 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/113970
Bus arbitration apparatus and bus arbitration method Apr 25, 2005 Issued
Array ( [id] => 6927449 [patent_doc_number] => 20050240706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Peripheral device control system' [patent_app_type] => utility [patent_app_number] => 11/111510 [patent_app_country] => US [patent_app_date] => 2005-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3279 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20050240706.pdf [firstpage_image] =>[orig_patent_app_number] => 11111510 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/111510
Peripheral device control system Apr 20, 2005 Abandoned
Array ( [id] => 5927839 [patent_doc_number] => 20060242351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Method and apparatus for loading instructions into high memory' [patent_app_type] => utility [patent_app_number] => 11/111180 [patent_app_country] => US [patent_app_date] => 2005-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20060242351.pdf [firstpage_image] =>[orig_patent_app_number] => 11111180 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/111180
Method and apparatus for loading instructions into high memory Apr 19, 2005 Abandoned
Array ( [id] => 192895 [patent_doc_number] => 07644221 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-01-05 [patent_title] => 'System interface unit' [patent_app_type] => utility [patent_app_number] => 11/103319 [patent_app_country] => US [patent_app_date] => 2005-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8718 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/644/07644221.pdf [firstpage_image] =>[orig_patent_app_number] => 11103319 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/103319
System interface unit Apr 10, 2005 Issued
Array ( [id] => 5861596 [patent_doc_number] => 20060230210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Method and apparatus for memory interface' [patent_app_type] => utility [patent_app_number] => 11/096182 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3982 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20060230210.pdf [firstpage_image] =>[orig_patent_app_number] => 11096182 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/096182
Method and apparatus for memory interface Mar 30, 2005 Issued
Array ( [id] => 465758 [patent_doc_number] => 07243177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-10 [patent_title] => 'Method and system for throttling data packets in a data transmission system' [patent_app_type] => utility [patent_app_number] => 11/095420 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6523 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/243/07243177.pdf [firstpage_image] =>[orig_patent_app_number] => 11095420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/095420
Method and system for throttling data packets in a data transmission system Mar 30, 2005 Issued
Array ( [id] => 423649 [patent_doc_number] => 07275125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Pipeline bit handling circuit and method for a bus bridge' [patent_app_type] => utility [patent_app_number] => 11/064744 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4504 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/275/07275125.pdf [firstpage_image] =>[orig_patent_app_number] => 11064744 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064744
Pipeline bit handling circuit and method for a bus bridge Feb 23, 2005 Issued
Array ( [id] => 534145 [patent_doc_number] => 07194567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Method and system for ordering requests at a bus interface' [patent_app_type] => utility [patent_app_number] => 11/064728 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4116 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194567.pdf [firstpage_image] =>[orig_patent_app_number] => 11064728 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064728
Method and system for ordering requests at a bus interface Feb 23, 2005 Issued
Array ( [id] => 571005 [patent_doc_number] => 07469312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-23 [patent_title] => 'Computer system bus bridge' [patent_app_type] => utility [patent_app_number] => 11/064568 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 8854 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/469/07469312.pdf [firstpage_image] =>[orig_patent_app_number] => 11064568 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064568
Computer system bus bridge Feb 23, 2005 Issued
Array ( [id] => 431309 [patent_doc_number] => 07269681 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-11 [patent_title] => 'Arrangement for receiving and transmitting PCI-X data according to selected data modes' [patent_app_type] => utility [patent_app_number] => 11/000062 [patent_app_country] => US [patent_app_date] => 2004-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7748 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269681.pdf [firstpage_image] =>[orig_patent_app_number] => 11000062 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000062
Arrangement for receiving and transmitting PCI-X data according to selected data modes Nov 30, 2004 Issued
Array ( [id] => 629777 [patent_doc_number] => 07136955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Expansion adapter supporting both PCI and AGP device functions' [patent_app_type] => utility [patent_app_number] => 10/980624 [patent_app_country] => US [patent_app_date] => 2004-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2707 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/136/07136955.pdf [firstpage_image] =>[orig_patent_app_number] => 10980624 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/980624
Expansion adapter supporting both PCI and AGP device functions Nov 2, 2004 Issued
Array ( [id] => 5806591 [patent_doc_number] => 20060092944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Methods and apparatuses to manage bandwidth mismatches between a sending device and a receiving device' [patent_app_type] => utility [patent_app_number] => 10/980505 [patent_app_country] => US [patent_app_date] => 2004-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9964 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20060092944.pdf [firstpage_image] =>[orig_patent_app_number] => 10980505 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/980505
Methods and apparatuses to manage bandwidth mismatches between a sending device and a receiving device Nov 1, 2004 Issued
Array ( [id] => 421262 [patent_doc_number] => 07277975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'Methods and apparatuses for decoupling a request from one or more solicited responses' [patent_app_type] => utility [patent_app_number] => 10/980736 [patent_app_country] => US [patent_app_date] => 2004-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11162 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/277/07277975.pdf [firstpage_image] =>[orig_patent_app_number] => 10980736 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/980736
Methods and apparatuses for decoupling a request from one or more solicited responses Nov 1, 2004 Issued
Array ( [id] => 5809237 [patent_doc_number] => 20060095592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Multi-channel memory architecture for daisy chained arrangements of nodes with bridging between memory channels' [patent_app_type] => utility [patent_app_number] => 10/977770 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6965 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095592.pdf [firstpage_image] =>[orig_patent_app_number] => 10977770 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/977770
Multi-channel memory architecture for daisy chained arrangements of nodes with bridging between memory channels Oct 28, 2004 Issued
Array ( [id] => 7589700 [patent_doc_number] => 07664903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Control unit with PCI and SCSI buses and computing system with electronic semiconductor disk' [patent_app_type] => utility [patent_app_number] => 10/944895 [patent_app_country] => US [patent_app_date] => 2004-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 53 [patent_no_of_words] => 15714 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/664/07664903.pdf [firstpage_image] =>[orig_patent_app_number] => 10944895 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/944895
Control unit with PCI and SCSI buses and computing system with electronic semiconductor disk Sep 20, 2004 Issued
Array ( [id] => 633278 [patent_doc_number] => 07133958 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-07 [patent_title] => 'Multiple personality I/O bus' [patent_app_type] => utility [patent_app_number] => 10/934039 [patent_app_country] => US [patent_app_date] => 2004-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/133/07133958.pdf [firstpage_image] =>[orig_patent_app_number] => 10934039 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/934039
Multiple personality I/O bus Sep 2, 2004 Issued
Array ( [id] => 553536 [patent_doc_number] => 07181557 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-20 [patent_title] => 'Single wire bus for connecting devices and methods of operating the same' [patent_app_type] => utility [patent_app_number] => 10/932347 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 20624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/181/07181557.pdf [firstpage_image] =>[orig_patent_app_number] => 10932347 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/932347
Single wire bus for connecting devices and methods of operating the same Aug 31, 2004 Issued
Array ( [id] => 921858 [patent_doc_number] => 07325082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-29 [patent_title] => 'System and method for guaranteeing transactional fairness among multiple requesters' [patent_app_type] => utility [patent_app_number] => 10/926226 [patent_app_country] => US [patent_app_date] => 2004-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4967 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/325/07325082.pdf [firstpage_image] =>[orig_patent_app_number] => 10926226 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/926226
System and method for guaranteeing transactional fairness among multiple requesters Aug 24, 2004 Issued
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