
Elias Mamo
Examiner (ID: 13802, Phone: (571)270-1726 , Office: P/2184 )
| Most Active Art Unit | 2184 |
| Art Unit(s) | 2184 |
| Total Applications | 1156 |
| Issued Applications | 950 |
| Pending Applications | 59 |
| Abandoned Applications | 174 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20323287
[patent_doc_number] => 20250335375
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-30
[patent_title] => Memory-Request Priority Up-Leveling
[patent_app_type] => utility
[patent_app_number] => 19/177996
[patent_app_country] => US
[patent_app_date] => 2025-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1126
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19177996
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/177996 | Memory-Request Priority Up-Leveling | Apr 13, 2025 | Pending |
Array
(
[id] => 20249671
[patent_doc_number] => 20250298540
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => REDUNDANT COMPUTING ACROSS PLANES
[patent_app_type] => utility
[patent_app_number] => 19/170136
[patent_app_country] => US
[patent_app_date] => 2025-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12676
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19170136
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/170136 | REDUNDANT COMPUTING ACROSS PLANES | Apr 3, 2025 | Pending |
Array
(
[id] => 20285035
[patent_doc_number] => 20250310277
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-02
[patent_title] => PACKET PROCESSING METHOD AND APPARATUS APPLIED TO DPU, COMPUTER DEVICE AND STORAGE MEDIUM
[patent_app_type] => utility
[patent_app_number] => 19/093749
[patent_app_country] => US
[patent_app_date] => 2025-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1403
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19093749
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/093749 | PACKET PROCESSING METHOD AND APPARATUS APPLIED TO DPU, COMPUTER DEVICE AND STORAGE MEDIUM | Mar 27, 2025 | Pending |
Array
(
[id] => 20181250
[patent_doc_number] => 20250265208
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-21
[patent_title] => ELECTRONIC CONTROL UNIT AND CONTROL METHOD
[patent_app_type] => utility
[patent_app_number] => 19/046249
[patent_app_country] => US
[patent_app_date] => 2025-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4137
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19046249
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/046249 | ELECTRONIC CONTROL UNIT AND CONTROL METHOD | Feb 4, 2025 | Pending |
Array
(
[id] => 20043015
[patent_doc_number] => 20250181237
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => Storage Optimization of CAT Table During Background Operations
[patent_app_type] => utility
[patent_app_number] => 19/044957
[patent_app_country] => US
[patent_app_date] => 2025-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1179
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19044957
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/044957 | Storage Optimization of CAT Table During Background Operations | Feb 3, 2025 | Pending |
Array
(
[id] => 20043306
[patent_doc_number] => 20250181528
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS
[patent_app_type] => utility
[patent_app_number] => 19/022389
[patent_app_country] => US
[patent_app_date] => 2025-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 41827
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19022389
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/022389 | COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS | Jan 14, 2025 | Pending |
Array
(
[id] => 20131064
[patent_doc_number] => 12373377
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-29
[patent_title] => Protocol-aware provisioning of resource over CXL fabrics
[patent_app_type] => utility
[patent_app_number] => 19/017419
[patent_app_country] => US
[patent_app_date] => 2025-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 79
[patent_figures_cnt] => 106
[patent_no_of_words] => 70932
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19017419
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/017419 | Protocol-aware provisioning of resource over CXL fabrics | Jan 10, 2025 | Issued |
Array
(
[id] => 20043305
[patent_doc_number] => 20250181527
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS
[patent_app_type] => utility
[patent_app_number] => 19/014838
[patent_app_country] => US
[patent_app_date] => 2025-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 42944
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19014838
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/014838 | COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS | Jan 8, 2025 | Pending |
Array
(
[id] => 20221723
[patent_doc_number] => 20250284654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-11
[patent_title] => System for Multiple PCIe Hosts to Share SR-IOV Devices with Standard Host Drivers
[patent_app_type] => utility
[patent_app_number] => 19/011747
[patent_app_country] => US
[patent_app_date] => 2025-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8274
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19011747
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/011747 | System for Multiple PCIe Hosts to Share SR-IOV Devices with Standard Host Drivers | Jan 6, 2025 | Pending |
Array
(
[id] => 20009662
[patent_doc_number] => 20250147884
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-08
[patent_title] => APPARATUS FOR MANAGING CACHE LOSS AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 19/003514
[patent_app_country] => US
[patent_app_date] => 2024-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8151
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19003514
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/003514 | APPARATUS FOR MANAGING CACHE LOSS AND OPERATION METHOD THEREOF | Dec 26, 2024 | Pending |
Array
(
[id] => 19892030
[patent_doc_number] => 20250117342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-10
[patent_title] => APPARATUS AND METHOD USING PLURALITY OF PHYSICAL ADDRESS SPACES
[patent_app_type] => utility
[patent_app_number] => 18/987328
[patent_app_country] => US
[patent_app_date] => 2024-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 24242
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18987328
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/987328 | APPARATUS AND METHOD USING PLURALITY OF PHYSICAL ADDRESS SPACES | Dec 18, 2024 | Pending |
Array
(
[id] => 19891836
[patent_doc_number] => 20250117148
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-10
[patent_title] => THRESHOLD VOLTAGE BIN CALIBRATION AT MEMORY DEVICE POWER UP
[patent_app_type] => utility
[patent_app_number] => 18/982255
[patent_app_country] => US
[patent_app_date] => 2024-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7041
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18982255
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/982255 | THRESHOLD VOLTAGE BIN CALIBRATION AT MEMORY DEVICE POWER UP | Dec 15, 2024 | Pending |
Array
(
[id] => 20152155
[patent_doc_number] => 20250251993
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-07
[patent_title] => SHARED RESOURCE MANAGEMENT FOR MULTI-CORE SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/981503
[patent_app_country] => US
[patent_app_date] => 2024-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5937
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18981503
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/981503 | SHARED RESOURCE MANAGEMENT FOR MULTI-CORE SYSTEM | Dec 13, 2024 | Pending |
Array
(
[id] => 20764600
[patent_doc_number] => 20260161584
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-06-11
[patent_title] => ACCELERATED COMPUTATION OF DIRECT MEMORY ACCESS SCATTER CONTEXT FOR GET RESPONSE
[patent_app_type] => utility
[patent_app_number] => 18/977625
[patent_app_country] => US
[patent_app_date] => 2024-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6728
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18977625
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/977625 | ACCELERATED COMPUTATION OF DIRECT MEMORY ACCESS SCATTER CONTEXT FOR GET RESPONSE | Dec 10, 2024 | Pending |
Array
(
[id] => 20052163
[patent_doc_number] => 20250190385
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-12
[patent_title] => ELECTRONIC SYSTEM HAVING AN INTEGRATED MASTER CIRCUIT AND AN INTEGRATED SLAVE CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/974946
[patent_app_country] => US
[patent_app_date] => 2024-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1184
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18974946
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/974946 | Electronic system having an integrated master circuit and an integrated slave circuit | Dec 9, 2024 | Issued |
Array
(
[id] => 20043052
[patent_doc_number] => 20250181274
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => DYNAMIC SELECTION OF CORES FOR PROCESSING RESPONSES
[patent_app_type] => utility
[patent_app_number] => 18/970574
[patent_app_country] => US
[patent_app_date] => 2024-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2346
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18970574
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/970574 | DYNAMIC SELECTION OF CORES FOR PROCESSING RESPONSES | Dec 4, 2024 | Pending |
Array
(
[id] => 20731994
[patent_doc_number] => 12639252
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-26
[patent_title] => Control chip, operating circuit, and interface simulation method
[patent_app_type] => utility
[patent_app_number] => 18/963967
[patent_app_country] => US
[patent_app_date] => 2024-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18963967
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/963967 | Control chip, operating circuit, and interface simulation method | Nov 28, 2024 | Issued |
Array
(
[id] => 20035071
[patent_doc_number] => 20250173293
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-29
[patent_title] => HUB DEVICE AND CONTROL SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/955302
[patent_app_country] => US
[patent_app_date] => 2024-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1076
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18955302
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/955302 | Hub device and control system | Nov 20, 2024 | Issued |
Array
(
[id] => 20043304
[patent_doc_number] => 20250181526
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS
[patent_app_type] => utility
[patent_app_number] => 18/955468
[patent_app_country] => US
[patent_app_date] => 2024-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 41802
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -34
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18955468
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/955468 | COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS | Nov 20, 2024 | Pending |
Array
(
[id] => 20915903
[patent_doc_number] => 12712759
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-08-18
[patent_title] => Subscriber station and method for deterministic communication in a serial bus system
[patent_app_type] => utility
[patent_app_number] => 18/947845
[patent_app_country] => US
[patent_app_date] => 2024-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4320
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18947845
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/947845 | SUBSCRIBER STATION AND METHOD FOR DETERMINISTIC COMMUNICATION IN A SERIAL BUS SYSTEM | Nov 13, 2024 | Pending |